   1              		.cpu cortex-m0plus
   2              		.fpu softvfp
   3              		.eabi_attribute 20, 1
   4              		.eabi_attribute 21, 1
   5              		.eabi_attribute 23, 3
   6              		.eabi_attribute 24, 1
   7              		.eabi_attribute 25, 1
   8              		.eabi_attribute 26, 1
   9              		.eabi_attribute 30, 6
  10              		.eabi_attribute 34, 0
  11              		.eabi_attribute 18, 4
  12              		.code	16
  13              		.file	"system_MKL16Z4.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.global	SystemCoreClock
  18              		.section	.data.SystemCoreClock,"aw",%progbits
  19              		.align	2
  22              	SystemCoreClock:
  23 0000 00004001 		.word	20971520
  24              		.section	.text.SystemInit,"ax",%progbits
  25              		.align	2
  26              		.global	SystemInit
  27              		.code	16
  28              		.thumb_func
  30              	SystemInit:
  31              	.LFB33:
  32              		.file 1 "../Project_Settings/Startup_Code/system_MKL16Z4.c"
   1:../Project_Settings/Startup_Code/system_MKL16Z4.c **** /*
   2:../Project_Settings/Startup_Code/system_MKL16Z4.c **** ** ###################################################################
   3:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Processors:          MKL16Z128VFM4
   4:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z64VFM4
   5:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z32VFM4
   6:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z128VFT4
   7:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z64VFT4
   8:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z32VFT4
   9:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z128VLH4
  10:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z64VH4
  11:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          MKL16Z32VLH4
  12:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  13:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Compilers:           Keil ARM C/C++ Compiler
  14:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          Freescale C/C++ for Embedded ARM
  15:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          GNU C Compiler
  16:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          GNU C Compiler - CodeSourcery Sourcery G++
  17:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          IAR ANSI C/C++ Compiler for ARM
  18:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  19:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Reference manuals:   KL26P121M48SF4RM Rev. 3.2, October 2013
  20:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **                          KL16P121M48SF4RM, Rev.2, Dec 2012
  21:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  22:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Version:             rev. 1.3, 2014-05-27
  23:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Build:               b140617
  24:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  25:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Abstract:
  26:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         Provides a system configuration function and a global variable that
  27:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         contains the system frequency. It configures the device and initializes
  28:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         the oscillator (PLL) that is part of the microcontroller device.
  29:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  30:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  31:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     All rights reserved.
  32:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  33:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Redistribution and use in source and binary forms, with or without modification,
  34:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     are permitted provided that the following conditions are met:
  35:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  36:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     o Redistributions of source code must retain the above copyright notice, this list
  37:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **       of conditions and the following disclaimer.
  38:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  39:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     o Redistributions in binary form must reproduce the above copyright notice, this
  40:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **       list of conditions and the following disclaimer in the documentation and/or
  41:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **       other materials provided with the distribution.
  42:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  43:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  44:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **       contributors may be used to endorse or promote products derived from this
  45:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **       software without specific prior written permission.
  46:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  47:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  48:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  49:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  50:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  51:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  52:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  53:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  54:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  55:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  56:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  57:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  58:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     http:                 www.freescale.com
  59:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     mail:                 support@freescale.com
  60:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  61:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     Revisions:
  62:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     - rev. 1.0 (2012-12-12)
  63:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         Initial version.
  64:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     - rev. 1.1 (2013-04-05)
  65:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         Changed start of doxygen comment.
  66:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     - rev. 1.2 (2013-04-12)
  67:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         SystemInit function fixed for clock configuration 1.
  68:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         Name of the interrupt num. 31 updated to reflect proper function.
  69:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **     - rev. 1.3 (2014-05-27)
  70:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         Updated to Kinetis SDK support standard.
  71:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **         MCG OSC clock select supported (MCG_C7[OSCSEL]).
  72:../Project_Settings/Startup_Code/system_MKL16Z4.c **** **
  73:../Project_Settings/Startup_Code/system_MKL16Z4.c **** ** ###################################################################
  74:../Project_Settings/Startup_Code/system_MKL16Z4.c **** */
  75:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
  76:../Project_Settings/Startup_Code/system_MKL16Z4.c **** /*!
  77:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  * @file MKL16Z4
  78:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  * @version 1.3
  79:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  * @date 2014-05-27
  80:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  * @brief Device specific configuration file for MKL16Z4 (implementation file)
  81:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  *
  82:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  * Provides a system configuration function and a global variable that contains
  83:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  * the system frequency. It configures the device and initializes the oscillator
  84:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  * (PLL) that is part of the microcontroller device.
  85:../Project_Settings/Startup_Code/system_MKL16Z4.c ****  */
  86:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
  87:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #include <stdint.h>
  88:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #include "MKL16Z4.h"
  89:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
  90:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
  91:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
  92:../Project_Settings/Startup_Code/system_MKL16Z4.c **** /* ----------------------------------------------------------------------------
  93:../Project_Settings/Startup_Code/system_MKL16Z4.c ****    -- Core clock
  94:../Project_Settings/Startup_Code/system_MKL16Z4.c ****    ---------------------------------------------------------------------------- */
  95:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
  96:../Project_Settings/Startup_Code/system_MKL16Z4.c **** uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
  97:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
  98:../Project_Settings/Startup_Code/system_MKL16Z4.c **** /* ----------------------------------------------------------------------------
  99:../Project_Settings/Startup_Code/system_MKL16Z4.c ****    -- SystemInit()
 100:../Project_Settings/Startup_Code/system_MKL16Z4.c ****    ---------------------------------------------------------------------------- */
 101:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 102:../Project_Settings/Startup_Code/system_MKL16Z4.c **** void SystemInit (void) {
  33              		.loc 1 102 0
  34              		.cfi_startproc
  35 0000 80B5     		push	{r7, lr}
  36              		.cfi_def_cfa_offset 8
  37              		.cfi_offset 7, -8
  38              		.cfi_offset 14, -4
  39 0002 00AF     		add	r7, sp, #0
  40              		.cfi_def_cfa_register 7
 103:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 104:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if (DISABLE_WDOG)
 105:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
 106:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM->COPC = (uint32_t)0x00u;
 107:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif /* (DISABLE_WDOG) */
 108:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #ifdef RTC_CR_VALUE
 109:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
 110:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
 111:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_C
 112:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
 113:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
 114:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 115:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif
 116:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 117:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Power mode protection initialization */
 118:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #ifdef SMC_PMPROT_VALUE
 119:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SMC->PMPROT = SMC_PMPROT_VALUE;
  41              		.loc 1 119 0
  42 0004 2B4B     		ldr	r3, .L4
  43 0006 2A22     		mov	r2, #42
  44 0008 1A70     		strb	r2, [r3]
 120:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif
 121:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 122:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* System clock initialization */
 123:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Internal reference clock trim initialization */
 124:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if defined(SLOW_TRIM_ADDRESS)
 125:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volat
 126:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
 127:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif /* defined(SLOW_TRIM_ADDRESS) */
 128:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #if defined(SLOW_FINE_TRIM_ADDRESS)
 129:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4
 130:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif
 131:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #if defined(FAST_TRIM_ADDRESS)
 132:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM
 133:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif
 134:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #if defined(FAST_FINE_TRIM_ADDRESS)
 135:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTR
 136:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
 137:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if defined(SLOW_TRIM_ADDRESS)
 138:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 139:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif /* defined(SLOW_TRIM_ADDRESS) */
 140:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 141:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Set system prescalers and clock sources */
 142:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM->CLKDIV1 = SIM_CLKDIV1_VALUE;    /* Set system prescalers */
  45              		.loc 1 142 0
  46 000a 2B4A     		ldr	r2, .L4+4
  47 000c 2B4B     		ldr	r3, .L4+8
  48 000e 0021     		mov	r1, #0
  49 0010 D150     		str	r1, [r2, r3]
 143:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SIM_SOPT1_VALUE) & (SIM
  50              		.loc 1 143 0
  51 0012 294B     		ldr	r3, .L4+4
  52 0014 284A     		ldr	r2, .L4+4
  53 0016 1268     		ldr	r2, [r2]
  54 0018 C021     		mov	r1, #192
  55 001a 0903     		lsl	r1, r1, #12
  56 001c 0A43     		orr	r2, r1
  57 001e 1A60     		str	r2, [r3]
 144:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SIM_SOPT2_VALUE) & (SIM
  58              		.loc 1 144 0
  59 0020 254A     		ldr	r2, .L4+4
  60 0022 2549     		ldr	r1, .L4+4
  61 0024 264B     		ldr	r3, .L4+12
  62 0026 C958     		ldr	r1, [r1, r3]
  63 0028 264B     		ldr	r3, .L4+16
  64 002a 1940     		and	r1, r3
  65 002c 244B     		ldr	r3, .L4+12
  66 002e D150     		str	r1, [r2, r3]
 145:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_TPMSRC_MASK))) | ((SIM_SOPT2_VALUE) & (SIM_SO
  67              		.loc 1 145 0
  68 0030 214A     		ldr	r2, .L4+4
  69 0032 2149     		ldr	r1, .L4+4
  70 0034 224B     		ldr	r3, .L4+12
  71 0036 C958     		ldr	r1, [r1, r3]
  72 0038 234B     		ldr	r3, .L4+20
  73 003a 0B40     		and	r3, r1
  74 003c 8021     		mov	r1, #128
  75 003e 4904     		lsl	r1, r1, #17
  76 0040 1943     		orr	r1, r3
  77 0042 1F4B     		ldr	r3, .L4+12
  78 0044 D150     		str	r1, [r2, r3]
 146:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
 147:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Set MCG and OSC */
 148:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if  ((((OSC0_CR_VALUE) & OSC0_CR_ERCLKEN_MASK) != 0x00U) || ((((MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_M
 149:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* SIM_SCGC5: PORTA=1 */
 150:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
 151:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* PORTA_PCR18: ISF=0,MUX=0 */
 152:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 153:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
 154:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* PORTA_PCR19: ISF=0,MUX=0 */
 155:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 156:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 157:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif
 158:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->SC = MCG_SC_VALUE;              /* Set SC (fast clock internal reference divider) */
  79              		.loc 1 158 0
  80 0046 214B     		ldr	r3, .L4+24
  81 0048 0022     		mov	r2, #0
  82 004a 1A72     		strb	r2, [r3, #8]
 159:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C1 = MCG_C1_VALUE;              /* Set C1 (clock source selection, FLL ext. reference divide
  83              		.loc 1 159 0
  84 004c 1F4B     		ldr	r3, .L4+24
  85 004e 0622     		mov	r2, #6
  86 0050 1A70     		strb	r2, [r3]
 160:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Check that the source of the FLL reference clock is the requested one. */
 161:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if (((MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
 162:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
  87              		.loc 1 162 0
  88 0052 C046     		mov	r8, r8
  89              	.L2:
  90              		.loc 1 162 0 is_stmt 0 discriminator 1
  91 0054 1D4B     		ldr	r3, .L4+24
  92 0056 9B79     		ldrb	r3, [r3, #6]
  93 0058 DBB2     		uxtb	r3, r3
  94 005a 1A1C     		mov	r2, r3
  95 005c 1023     		mov	r3, #16
  96 005e 1340     		and	r3, r2
  97 0060 F8D0     		beq	.L2
 163:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     }
 164:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   } else {
 165:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
 166:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     }
 167:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 168:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_M
  98              		.loc 1 168 0 is_stmt 1
  99 0062 1A4B     		ldr	r3, .L4+24
 100 0064 194A     		ldr	r2, .L4+24
 101 0066 5278     		ldrb	r2, [r2, #1]
 102 0068 D2B2     		uxtb	r2, r2
 103 006a 6421     		mov	r1, #100
 104 006c 8A43     		bic	r2, r1
 105 006e D2B2     		uxtb	r2, r2
 106 0070 2421     		mov	r1, #36
 107 0072 0A43     		orr	r2, r1
 108 0074 D2B2     		uxtb	r2, r2
 109 0076 5A70     		strb	r2, [r3, #1]
 169:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C4 = ((MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & 
 110              		.loc 1 169 0
 111 0078 144B     		ldr	r3, .L4+24
 112 007a 144A     		ldr	r2, .L4+24
 113 007c D278     		ldrb	r2, [r2, #3]
 114 007e D1B2     		uxtb	r1, r2
 115 0080 1F22     		mov	r2, #31
 116 0082 0A40     		and	r2, r1
 117 0084 D2B2     		uxtb	r2, r2
 118 0086 DA70     		strb	r2, [r3, #3]
 170:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   OSC0->CR = OSC0_CR_VALUE;            /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) *
 119              		.loc 1 170 0
 120 0088 114B     		ldr	r3, .L4+28
 121 008a 8022     		mov	r2, #128
 122 008c 1A70     		strb	r2, [r3]
 171:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C7 = MCG_C7_VALUE;              /* Set C7 (OSC Clock Select) */
 123              		.loc 1 171 0
 124 008e 0F4B     		ldr	r3, .L4+24
 125 0090 0022     		mov	r2, #0
 126 0092 1A73     		strb	r2, [r3, #12]
 172:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #if (MCG_MODE == MCG_MODE_BLPI)
 173:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* BLPI specific */
 174:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
 175:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif
 176:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 177:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #else /* MCG_MODE */
 178:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Set MCG and OSC */
 179:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if  (((OSC0_CR_VALUE) & OSC0_CR_ERCLKEN_MASK) != 0x00U) || (((MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) 
 180:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* SIM_SCGC5: PORTA=1 */
 181:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
 182:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* PORTA_PCR18: ISF=0,MUX=0 */
 183:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 184:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
 185:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* PORTA_PCR19: ISF=0,MUX=0 */
 186:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 187:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 188:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif
 189:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->SC = MCG_SC_VALUE;              /* Set SC (fast clock internal reference divider) */
 190:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_M
 191:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   OSC0->CR = OSC0_CR_VALUE;            /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) *
 192:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C7 = MCG_C7_VALUE;              /* Set C7 (OSC Clock Select) */
 193:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #if (MCG_MODE == MCG_MODE_PEE)
 194:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C1 = (MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. referen
 195:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #else
 196:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C1 = MCG_C1_VALUE;              /* Set C1 (clock source selection, FLL ext. reference divide
 197:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif
 198:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0U) {
 199:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
 200:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     }
 201:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 202:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Check that the source of the FLL reference clock is the requested one. */
 203:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if (((MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
 204:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
 205:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     }
 206:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   } else {
 207:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
 208:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     }
 209:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 210:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C4 = ((MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 &
 211:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif /* MCG_MODE */
 212:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 213:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* Common for all MCG modes */
 214:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 215:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUT
 216:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C5 = (MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL refe
 127              		.loc 1 216 0
 128 0094 0D4B     		ldr	r3, .L4+24
 129 0096 0022     		mov	r2, #0
 130 0098 1A71     		strb	r2, [r3, #4]
 217:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C6 = (MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.)
 131              		.loc 1 217 0
 132 009a 0C4B     		ldr	r3, .L4+24
 133 009c 0022     		mov	r2, #0
 134 009e 5A71     		strb	r2, [r3, #5]
 218:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if ((MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
 219:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
 220:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 221:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* BLPE, PEE and PBE MCG mode specific */
 222:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 223:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if (MCG_MODE == MCG_MODE_BLPE)
 224:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
 225:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
 226:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
 227:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
 228:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 229:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #if (MCG_MODE == MCG_MODE_PEE)
 230:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
 231:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   #endif
 232:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif
 233:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
 234:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
 135              		.loc 1 234 0
 136 00a0 C046     		mov	r8, r8
 137              	.L3:
 138              		.loc 1 234 0 is_stmt 0 discriminator 1
 139 00a2 0A4B     		ldr	r3, .L4+24
 140 00a4 9B79     		ldrb	r3, [r3, #6]
 141 00a6 DBB2     		uxtb	r3, r3
 142 00a8 1A1C     		mov	r2, r3
 143 00aa 0C23     		mov	r3, #12
 144 00ac 1340     		and	r3, r2
 145 00ae F8D1     		bne	.L3
 235:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 236:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
 237:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected 
 238:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 239:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
 240:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected 
 241:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 242:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #elif (MCG_MODE == MCG_MODE_PEE)
 243:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
 244:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 245:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_BLPE))
 246:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected 
 247:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 248:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif
 249:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #if (((SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
 250:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
 251:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
 252:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 253:../Project_Settings/Startup_Code/system_MKL16Z4.c **** #endif
 254:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 255:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   /* PLL loss of lock interrupt request initialization */
 256:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if (((MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
 257:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
 258:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   }
 259:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 260:../Project_Settings/Startup_Code/system_MKL16Z4.c **** }
 146              		.loc 1 260 0 is_stmt 1
 147 00b0 BD46     		mov	sp, r7
 148              		@ sp needed
 149 00b2 80BD     		pop	{r7, pc}
 150              	.L5:
 151              		.align	2
 152              	.L4:
 153 00b4 00E00740 		.word	1074257920
 154 00b8 00700440 		.word	1074032640
 155 00bc 44100000 		.word	4164
 156 00c0 04100000 		.word	4100
 157 00c4 FFFFFEFF 		.word	-65537
 158 00c8 FFFFFFFC 		.word	-50331649
 159 00cc 00400640 		.word	1074151424
 160 00d0 00500640 		.word	1074155520
 161              		.cfi_endproc
 162              	.LFE33:
 164              		.global	__aeabi_uidiv
 165              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
 166              		.align	2
 167              		.global	SystemCoreClockUpdate
 168              		.code	16
 169              		.thumb_func
 171              	SystemCoreClockUpdate:
 172              	.LFB34:
 261:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 262:../Project_Settings/Startup_Code/system_MKL16Z4.c **** /* ----------------------------------------------------------------------------
 263:../Project_Settings/Startup_Code/system_MKL16Z4.c ****    -- SystemCoreClockUpdate()
 264:../Project_Settings/Startup_Code/system_MKL16Z4.c ****    ---------------------------------------------------------------------------- */
 265:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 266:../Project_Settings/Startup_Code/system_MKL16Z4.c **** void SystemCoreClockUpdate (void) {
 173              		.loc 1 266 0
 174              		.cfi_startproc
 175 0000 80B5     		push	{r7, lr}
 176              		.cfi_def_cfa_offset 8
 177              		.cfi_offset 7, -8
 178              		.cfi_offset 14, -4
 179 0002 82B0     		sub	sp, sp, #8
 180              		.cfi_def_cfa_offset 16
 181 0004 00AF     		add	r7, sp, #0
 182              		.cfi_def_cfa_register 7
 267:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 268:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG modul
 269:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   uint16_t Divider;
 270:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 271:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
 183              		.loc 1 271 0
 184 0006 944B     		ldr	r3, .L41
 185 0008 1B78     		ldrb	r3, [r3]
 186 000a DBB2     		uxtb	r3, r3
 187 000c 1A1C     		mov	r2, r3
 188 000e C023     		mov	r3, #192
 189 0010 1340     		and	r3, r2
 190 0012 00D0     		beq	.LCB142
 191 0014 D1E0     		b	.L7	@long jump
 192              	.LCB142:
 272:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     /* Output of FLL or PLL is selected */
 273:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
 193              		.loc 1 273 0
 194 0016 904B     		ldr	r3, .L41
 195 0018 5B79     		ldrb	r3, [r3, #5]
 196 001a DBB2     		uxtb	r3, r3
 197 001c 1A1C     		mov	r2, r3
 198 001e 4023     		mov	r3, #64
 199 0020 1340     		and	r3, r2
 200 0022 00D0     		beq	.LCB150
 201 0024 A7E0     		b	.L8	@long jump
 202              	.LCB150:
 274:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       /* FLL is selected */
 275:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
 203              		.loc 1 275 0
 204 0026 8C4B     		ldr	r3, .L41
 205 0028 1B78     		ldrb	r3, [r3]
 206 002a DBB2     		uxtb	r3, r3
 207 002c 1A1C     		mov	r2, r3
 208 002e 0423     		mov	r3, #4
 209 0030 1340     		and	r3, r2
 210 0032 4FD1     		bne	.L9
 276:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         /* External reference clock is selected */
 277:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
 211              		.loc 1 277 0
 212 0034 884B     		ldr	r3, .L41
 213 0036 1B7B     		ldrb	r3, [r3, #12]
 214 0038 DBB2     		uxtb	r3, r3
 215 003a 1A1C     		mov	r2, r3
 216 003c 0123     		mov	r3, #1
 217 003e 1340     		and	r3, r2
 218 0040 02D1     		bne	.L10
 278:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
 219              		.loc 1 278 0
 220 0042 864B     		ldr	r3, .L41+4
 221 0044 7B60     		str	r3, [r7, #4]
 222 0046 02E0     		b	.L11
 223              	.L10:
 279:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         } else {
 280:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
 224              		.loc 1 280 0
 225 0048 8023     		mov	r3, #128
 226 004a 1B02     		lsl	r3, r3, #8
 227 004c 7B60     		str	r3, [r7, #4]
 228              	.L11:
 281:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         }
 282:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U))
 229              		.loc 1 282 0
 230 004e 824B     		ldr	r3, .L41
 231 0050 5B78     		ldrb	r3, [r3, #1]
 232 0052 DBB2     		uxtb	r3, r3
 233 0054 1A1C     		mov	r2, r3
 234 0056 3023     		mov	r3, #48
 235 0058 1340     		and	r3, r2
 236 005a 27D0     		beq	.L12
 237              		.loc 1 282 0 is_stmt 0 discriminator 1
 238 005c 7E4B     		ldr	r3, .L41
 239 005e 1B7B     		ldrb	r3, [r3, #12]
 240 0060 DBB2     		uxtb	r3, r3
 241 0062 1A1C     		mov	r2, r3
 242 0064 0123     		mov	r3, #1
 243 0066 1340     		and	r3, r2
 244 0068 20D1     		bne	.L12
 283:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
 245              		.loc 1 283 0 is_stmt 1
 246 006a 7B4B     		ldr	r3, .L41
 247 006c 1B78     		ldrb	r3, [r3]
 248 006e DBB2     		uxtb	r3, r3
 249 0070 1A1C     		mov	r2, r3
 250 0072 3823     		mov	r3, #56
 251 0074 1340     		and	r3, r2
 252 0076 302B     		cmp	r3, #48
 253 0078 06D0     		beq	.L14
 254 007a 382B     		cmp	r3, #56
 255 007c 09D1     		bne	.L40
 284:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           case 0x38U:
 285:../Project_Settings/Startup_Code/system_MKL16Z4.c ****             Divider = 1536U;
 256              		.loc 1 285 0
 257 007e BB1C     		add	r3, r7, #2
 258 0080 C022     		mov	r2, #192
 259 0082 D200     		lsl	r2, r2, #3
 260 0084 1A80     		strh	r2, [r3]
 286:../Project_Settings/Startup_Code/system_MKL16Z4.c ****             break;
 261              		.loc 1 286 0
 262 0086 10E0     		b	.L16
 263              	.L14:
 287:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           case 0x30U:
 288:../Project_Settings/Startup_Code/system_MKL16Z4.c ****             Divider = 1280U;
 264              		.loc 1 288 0
 265 0088 BB1C     		add	r3, r7, #2
 266 008a A022     		mov	r2, #160
 267 008c D200     		lsl	r2, r2, #3
 268 008e 1A80     		strh	r2, [r3]
 289:../Project_Settings/Startup_Code/system_MKL16Z4.c ****             break;
 269              		.loc 1 289 0
 270 0090 0BE0     		b	.L16
 271              	.L40:
 290:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           default:
 291:../Project_Settings/Startup_Code/system_MKL16Z4.c ****             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 272              		.loc 1 291 0
 273 0092 714B     		ldr	r3, .L41
 274 0094 1B78     		ldrb	r3, [r3]
 275 0096 DBB2     		uxtb	r3, r3
 276 0098 1A1C     		mov	r2, r3
 277 009a 3823     		mov	r3, #56
 278 009c 1340     		and	r3, r2
 279 009e DB08     		lsr	r3, r3, #3
 280 00a0 2022     		mov	r2, #32
 281 00a2 9A40     		lsl	r2, r2, r3
 282 00a4 BB1C     		add	r3, r7, #2
 283 00a6 1A80     		strh	r2, [r3]
 292:../Project_Settings/Startup_Code/system_MKL16Z4.c ****             break;
 284              		.loc 1 292 0
 285 00a8 C046     		mov	r8, r8
 286              	.L16:
 293:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           }
 294:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
 287              		.loc 1 294 0
 288 00aa 0AE0     		b	.L17
 289              	.L12:
 295:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 290              		.loc 1 295 0
 291 00ac 6A4B     		ldr	r3, .L41
 292 00ae 1B78     		ldrb	r3, [r3]
 293 00b0 DBB2     		uxtb	r3, r3
 294 00b2 1A1C     		mov	r2, r3
 295 00b4 3823     		mov	r3, #56
 296 00b6 1340     		and	r3, r2
 297 00b8 DB08     		lsr	r3, r3, #3
 298 00ba 0122     		mov	r2, #1
 299 00bc 9A40     		lsl	r2, r2, r3
 300 00be BB1C     		add	r3, r7, #2
 301 00c0 1A80     		strh	r2, [r3]
 302              	.L17:
 296:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         }
 297:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
 303              		.loc 1 297 0
 304 00c2 BB1C     		add	r3, r7, #2
 305 00c4 1B88     		ldrh	r3, [r3]
 306 00c6 7868     		ldr	r0, [r7, #4]
 307 00c8 191C     		mov	r1, r3
 308 00ca FFF7FEFF 		bl	__aeabi_uidiv
 309 00ce 031C     		mov	r3, r0
 310 00d0 7B60     		str	r3, [r7, #4]
 311 00d2 02E0     		b	.L18
 312              	.L9:
 298:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
 299:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
 313              		.loc 1 299 0
 314 00d4 8023     		mov	r3, #128
 315 00d6 1B02     		lsl	r3, r3, #8
 316 00d8 7B60     		str	r3, [r7, #4]
 317              	.L18:
 300:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
 301:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       /* Select correct multiplier to calculate the MCG output clock  */
 302:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 318              		.loc 1 302 0
 319 00da 5F4B     		ldr	r3, .L41
 320 00dc DB78     		ldrb	r3, [r3, #3]
 321 00de DBB2     		uxtb	r3, r3
 322 00e0 1A1C     		mov	r2, r3
 323 00e2 E023     		mov	r3, #224
 324 00e4 1340     		and	r3, r2
 325 00e6 602B     		cmp	r3, #96
 326 00e8 27D0     		beq	.L20
 327 00ea 06D8     		bhi	.L21
 328 00ec 202B     		cmp	r3, #32
 329 00ee 16D0     		beq	.L22
 330 00f0 402B     		cmp	r3, #64
 331 00f2 1BD0     		beq	.L23
 332 00f4 002B     		cmp	r3, #0
 333 00f6 0BD0     		beq	.L24
 303:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0x00U:
 304:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 640U;
 305:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 306:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0x20U:
 307:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 1280U;
 308:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 309:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0x40U:
 310:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 1920U;
 311:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 312:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0x60U:
 313:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 2560U;
 314:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 315:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0x80U:
 316:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 732U;
 317:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 318:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0xA0U:
 319:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 1464U;
 320:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 321:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0xC0U:
 322:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 2197U;
 323:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 324:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         case 0xE0U:
 325:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 2929U;
 326:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 327:../Project_Settings/Startup_Code/system_MKL16Z4.c ****         default:
 328:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 334              		.loc 1 328 0
 335 00f8 3CE0     		b	.L30
 336              	.L21:
 302:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 337              		.loc 1 302 0
 338 00fa A02B     		cmp	r3, #160
 339 00fc 2AD0     		beq	.L25
 340 00fe 02D8     		bhi	.L26
 341 0100 802B     		cmp	r3, #128
 342 0102 21D0     		beq	.L27
 343              		.loc 1 328 0
 344 0104 36E0     		b	.L30
 345              	.L26:
 302:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 346              		.loc 1 302 0
 347 0106 C02B     		cmp	r3, #192
 348 0108 2AD0     		beq	.L28
 349 010a E02B     		cmp	r3, #224
 350 010c 2DD0     		beq	.L29
 351              		.loc 1 328 0
 352 010e 31E0     		b	.L30
 353              	.L24:
 304:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 640U;
 354              		.loc 1 304 0
 355 0110 7A68     		ldr	r2, [r7, #4]
 356 0112 131C     		mov	r3, r2
 357 0114 9B00     		lsl	r3, r3, #2
 358 0116 9B18     		add	r3, r3, r2
 359 0118 DB01     		lsl	r3, r3, #7
 360 011a 7B60     		str	r3, [r7, #4]
 305:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 361              		.loc 1 305 0
 362 011c 2AE0     		b	.L30
 363              	.L22:
 307:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 1280U;
 364              		.loc 1 307 0
 365 011e 7A68     		ldr	r2, [r7, #4]
 366 0120 131C     		mov	r3, r2
 367 0122 9B00     		lsl	r3, r3, #2
 368 0124 9B18     		add	r3, r3, r2
 369 0126 1B02     		lsl	r3, r3, #8
 370 0128 7B60     		str	r3, [r7, #4]
 308:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 371              		.loc 1 308 0
 372 012a 23E0     		b	.L30
 373              	.L23:
 310:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 1920U;
 374              		.loc 1 310 0
 375 012c 7A68     		ldr	r2, [r7, #4]
 376 012e 131C     		mov	r3, r2
 377 0130 1B01     		lsl	r3, r3, #4
 378 0132 9B1A     		sub	r3, r3, r2
 379 0134 DB01     		lsl	r3, r3, #7
 380 0136 7B60     		str	r3, [r7, #4]
 311:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 381              		.loc 1 311 0
 382 0138 1CE0     		b	.L30
 383              	.L20:
 313:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 2560U;
 384              		.loc 1 313 0
 385 013a 7A68     		ldr	r2, [r7, #4]
 386 013c 131C     		mov	r3, r2
 387 013e 9B00     		lsl	r3, r3, #2
 388 0140 9B18     		add	r3, r3, r2
 389 0142 5B02     		lsl	r3, r3, #9
 390 0144 7B60     		str	r3, [r7, #4]
 314:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 391              		.loc 1 314 0
 392 0146 15E0     		b	.L30
 393              	.L27:
 316:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 732U;
 394              		.loc 1 316 0
 395 0148 7B68     		ldr	r3, [r7, #4]
 396 014a B722     		mov	r2, #183
 397 014c 9200     		lsl	r2, r2, #2
 398 014e 5343     		mul	r3, r2
 399 0150 7B60     		str	r3, [r7, #4]
 317:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 400              		.loc 1 317 0
 401 0152 0FE0     		b	.L30
 402              	.L25:
 319:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 1464U;
 403              		.loc 1 319 0
 404 0154 7B68     		ldr	r3, [r7, #4]
 405 0156 B722     		mov	r2, #183
 406 0158 D200     		lsl	r2, r2, #3
 407 015a 5343     		mul	r3, r2
 408 015c 7B60     		str	r3, [r7, #4]
 320:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 409              		.loc 1 320 0
 410 015e 09E0     		b	.L30
 411              	.L28:
 322:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 2197U;
 412              		.loc 1 322 0
 413 0160 7B68     		ldr	r3, [r7, #4]
 414 0162 3F4A     		ldr	r2, .L41+8
 415 0164 5343     		mul	r3, r2
 416 0166 7B60     		str	r3, [r7, #4]
 323:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 417              		.loc 1 323 0
 418 0168 04E0     		b	.L30
 419              	.L29:
 325:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           MCGOUTClock *= 2929U;
 420              		.loc 1 325 0
 421 016a 7B68     		ldr	r3, [r7, #4]
 422 016c 3D4A     		ldr	r2, .L41+12
 423 016e 5343     		mul	r3, r2
 424 0170 7B60     		str	r3, [r7, #4]
 326:../Project_Settings/Startup_Code/system_MKL16Z4.c ****           break;
 425              		.loc 1 326 0
 426 0172 C046     		mov	r8, r8
 427              	.L30:
 428 0174 5FE0     		b	.L32
 429              	.L8:
 329:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       }
 330:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
 331:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       /* PLL is selected */
 332:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
 430              		.loc 1 332 0
 431 0176 384B     		ldr	r3, .L41
 432 0178 1B79     		ldrb	r3, [r3, #4]
 433 017a DBB2     		uxtb	r3, r3
 434 017c 1A1C     		mov	r2, r3
 435 017e 1F23     		mov	r3, #31
 436 0180 1340     		and	r3, r2
 437 0182 9AB2     		uxth	r2, r3
 438 0184 BB1C     		add	r3, r7, #2
 439 0186 0132     		add	r2, r2, #1
 440 0188 1A80     		strh	r2, [r3]
 333:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
 441              		.loc 1 333 0
 442 018a BB1C     		add	r3, r7, #2
 443 018c 1B88     		ldrh	r3, [r3]
 444 018e 3348     		ldr	r0, .L41+4
 445 0190 191C     		mov	r1, r3
 446 0192 FFF7FEFF 		bl	__aeabi_uidiv
 447 0196 031C     		mov	r3, r0
 448 0198 7B60     		str	r3, [r7, #4]
 334:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
 449              		.loc 1 334 0
 450 019a 2F4B     		ldr	r3, .L41
 451 019c 5B79     		ldrb	r3, [r3, #5]
 452 019e DBB2     		uxtb	r3, r3
 453 01a0 1A1C     		mov	r2, r3
 454 01a2 1F23     		mov	r3, #31
 455 01a4 1340     		and	r3, r2
 456 01a6 9AB2     		uxth	r2, r3
 457 01a8 BB1C     		add	r3, r7, #2
 458 01aa 1832     		add	r2, r2, #24
 459 01ac 1A80     		strh	r2, [r3]
 335:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
 460              		.loc 1 335 0
 461 01ae BB1C     		add	r3, r7, #2
 462 01b0 1A88     		ldrh	r2, [r3]
 463 01b2 7B68     		ldr	r3, [r7, #4]
 464 01b4 5343     		mul	r3, r2
 465 01b6 7B60     		str	r3, [r7, #4]
 466 01b8 3DE0     		b	.L32
 467              	.L7:
 336:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
 337:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
 468              		.loc 1 337 0
 469 01ba 274B     		ldr	r3, .L41
 470 01bc 1B78     		ldrb	r3, [r3]
 471 01be DBB2     		uxtb	r3, r3
 472 01c0 1A1C     		mov	r2, r3
 473 01c2 C023     		mov	r3, #192
 474 01c4 1340     		and	r3, r2
 475 01c6 402B     		cmp	r3, #64
 476 01c8 1ED1     		bne	.L33
 338:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     /* Internal reference clock is selected */
 339:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
 477              		.loc 1 339 0
 478 01ca 234B     		ldr	r3, .L41
 479 01cc 5B78     		ldrb	r3, [r3, #1]
 480 01ce DBB2     		uxtb	r3, r3
 481 01d0 1A1C     		mov	r2, r3
 482 01d2 0123     		mov	r3, #1
 483 01d4 1340     		and	r3, r2
 484 01d6 03D1     		bne	.L34
 340:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
 485              		.loc 1 340 0
 486 01d8 8023     		mov	r3, #128
 487 01da 1B02     		lsl	r3, r3, #8
 488 01dc 7B60     		str	r3, [r7, #4]
 489 01de 2AE0     		b	.L32
 490              	.L34:
 341:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
 342:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
 491              		.loc 1 342 0
 492 01e0 1D4B     		ldr	r3, .L41
 493 01e2 1B7A     		ldrb	r3, [r3, #8]
 494 01e4 DBB2     		uxtb	r3, r3
 495 01e6 1A1C     		mov	r2, r3
 496 01e8 0E23     		mov	r3, #14
 497 01ea 1340     		and	r3, r2
 498 01ec 5B08     		lsr	r3, r3, #1
 499 01ee 0122     		mov	r2, #1
 500 01f0 9A40     		lsl	r2, r2, r3
 501 01f2 BB1C     		add	r3, r7, #2
 502 01f4 1A80     		strh	r2, [r3]
 343:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock se
 503              		.loc 1 343 0
 504 01f6 BB1C     		add	r3, r7, #2
 505 01f8 1B88     		ldrh	r3, [r3]
 506 01fa 1B48     		ldr	r0, .L41+16
 507 01fc 191C     		mov	r1, r3
 508 01fe FFF7FEFF 		bl	__aeabi_uidiv
 509 0202 031C     		mov	r3, r0
 510 0204 7B60     		str	r3, [r7, #4]
 511 0206 16E0     		b	.L32
 512              	.L33:
 344:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
 345:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
 513              		.loc 1 345 0
 514 0208 134B     		ldr	r3, .L41
 515 020a 1B78     		ldrb	r3, [r3]
 516 020c DBB2     		uxtb	r3, r3
 517 020e 1A1C     		mov	r2, r3
 518 0210 C023     		mov	r3, #192
 519 0212 1340     		and	r3, r2
 520 0214 802B     		cmp	r3, #128
 521 0216 0DD1     		bne	.L36
 346:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     /* External reference clock is selected */
 347:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
 522              		.loc 1 347 0
 523 0218 0F4B     		ldr	r3, .L41
 524 021a 1B7B     		ldrb	r3, [r3, #12]
 525 021c DBB2     		uxtb	r3, r3
 526 021e 1A1C     		mov	r2, r3
 527 0220 0123     		mov	r3, #1
 528 0222 1340     		and	r3, r2
 529 0224 02D1     		bne	.L37
 348:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
 530              		.loc 1 348 0
 531 0226 0D4B     		ldr	r3, .L41+4
 532 0228 7B60     		str	r3, [r7, #4]
 533 022a 04E0     		b	.L32
 534              	.L37:
 349:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     } else {
 350:../Project_Settings/Startup_Code/system_MKL16Z4.c ****       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
 535              		.loc 1 350 0
 536 022c 8023     		mov	r3, #128
 537 022e 1B02     		lsl	r3, r3, #8
 538 0230 7B60     		str	r3, [r7, #4]
 539 0232 00E0     		b	.L32
 540              	.L36:
 351:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     }
 352:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
 353:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     /* Reserved value */
 354:../Project_Settings/Startup_Code/system_MKL16Z4.c ****     return;
 541              		.loc 1 354 0
 542 0234 0CE0     		b	.L6
 543              	.L32:
 355:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
 356:../Project_Settings/Startup_Code/system_MKL16Z4.c ****   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDI
 544              		.loc 1 356 0
 545 0236 0D4A     		ldr	r2, .L41+20
 546 0238 0D4B     		ldr	r3, .L41+24
 547 023a D358     		ldr	r3, [r2, r3]
 548 023c 1B0F     		lsr	r3, r3, #28
 549 023e 0133     		add	r3, r3, #1
 550 0240 7868     		ldr	r0, [r7, #4]
 551 0242 191C     		mov	r1, r3
 552 0244 FFF7FEFF 		bl	__aeabi_uidiv
 553 0248 031C     		mov	r3, r0
 554 024a 1A1C     		mov	r2, r3
 555 024c 094B     		ldr	r3, .L41+28
 556 024e 1A60     		str	r2, [r3]
 557              	.L6:
 357:../Project_Settings/Startup_Code/system_MKL16Z4.c **** 
 358:../Project_Settings/Startup_Code/system_MKL16Z4.c **** }
 558              		.loc 1 358 0
 559 0250 BD46     		mov	sp, r7
 560 0252 02B0     		add	sp, sp, #8
 561              		@ sp needed
 562 0254 80BD     		pop	{r7, pc}
 563              	.L42:
 564 0256 C046     		.align	2
 565              	.L41:
 566 0258 00400640 		.word	1074151424
 567 025c 00127A00 		.word	8000000
 568 0260 95080000 		.word	2197
 569 0264 710B0000 		.word	2929
 570 0268 00093D00 		.word	4000000
 571 026c 00700440 		.word	1074032640
 572 0270 44100000 		.word	4164
 573 0274 00000000 		.word	SystemCoreClock
 574              		.cfi_endproc
 575              	.LFE34:
 577              		.text
 578              	.Letext0:
 579              		.file 2 "e:\\logiciels\\freescale\\kinetis design studio v2.0.0\\toolchain\\arm-none-eabi\\include
 580              		.file 3 "../DSP/Processor/MKL16Z4.h"
DEFINED SYMBOLS
                            *ABS*:00000000 system_MKL16Z4.c
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:22     .data.SystemCoreClock:00000000 SystemCoreClock
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:19     .data.SystemCoreClock:00000000 $d
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:25     .text.SystemInit:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:30     .text.SystemInit:00000000 SystemInit
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:153    .text.SystemInit:000000b4 $d
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:166    .text.SystemCoreClockUpdate:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:171    .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
C:\Users\Thibaut\AppData\Local\Temp\cc3eHdcx.s:566    .text.SystemCoreClockUpdate:00000258 $d
                     .debug_frame:00000010 $d
                           .group:00000000 wm4.1.e04ac588437856bc6ef5393c7523eb9b
                           .group:00000000 wm4.stdint.h.10.90b695f550ca6cc3fb08fa83baf01e05
                           .group:00000000 wm4.MKL16Z4.h.90.cb29a163754e2b1b9e65515331ee8a16
                           .group:00000000 wm4.core_cm0plus.h.43.8a4a713129c4559638c90873d349aea7
                           .group:00000000 wm4.core_cmInstr.h.39.983ab10f37e3e59f2988e58e0e4c2ffe
                           .group:00000000 wm4.core_cm0plus.h.155.59f470bcbcb3497af7bb725005dd1359
                           .group:00000000 wm4.system_MKL16Z4.h.88.72b1d1936df247599ee4cea7d4cce2ba
                           .group:00000000 wm4.MKL16Z4.h.269.abf5f141593110fd4167c1d7382def80

UNDEFINED SYMBOLS
__aeabi_uidiv
