SRD Standelone programmation box: device.c File Reference

| SRD Standelone programmation box 2.0 (16/11/15 10:00:00) Documentation of the SRD standelone programmation box

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device.c File Reference

Source file for low level initialization and specific device feature. More...

`#include "device.h"`
Include dependency graph for device.c:

Go to the source code of this file.

## Functions

void | DeviceInit (void)
| Function to initialize the device clock. More...
void | DeviceClockSwitchDefaultFEI (void)
| Function to switch the processor clock on the FEI clock source. More...
void | DeviceClockSwitchHighPower (void)
| Function to switch the processor on the highest clock speed allowed. More...
void | LPM_Sleep (void)
| Function to switch the device in sleep mode. More...
void | LPM_DeepSleep (void)
| Function to switch the device in deep sleep mode. More...
void | LPM_VLPS (void)
| Function to switch the device in very low power mode. More...

## Detailed Description

Source file for low level initialization and specific device feature.

Author
  Thibaut LALUQUE 3D-Ouest

Date
  26/09/2014

Version
  1.0

All Right Reserved.

Definition in file device.c.

## Function Documentation

void DeviceClockSwitchDefaultFEI | ( | void |  | ) |

Function to switch the processor clock on the FEI clock source.

FEI : FLL Engaged Internal. In this mode the processor is running with a 21MHz clock.

Definition at line 84 of file device.c.

References tDeviceClock::busClockFreq, tDeviceClock::coreClockFreq, DeviceClock, tDeviceClock::ERCLK32KClockFreq, tDeviceClock::flashClockFreq, tDeviceClock::LowPowerOscillatorFreq, tDeviceClock::masterPeripheralClockFreq, tDeviceClock::MCGIRCLKClockFreq, tDeviceClock::OSCERCLKClockFreq, tDeviceClock::platformClockFreq, tDeviceClock::RtcClockOutFreq, and tDeviceClock::systemClockFreq.

Referenced by DeviceInit().

84 {
85
86 /*===Set oscillator to safe value ===*/
87 SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */
88 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
89 if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
90 PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
91 }
92
93 /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
94 SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
95 /* SIM_SOPT2: PLLFLLSEL=0 */
96 SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
97 /* SIM_SOPT1: OSC32KSEL=3 */
98 SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
99 /* SIM_SOPT2: TPMSRC=1 */
100 SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
101 SIM_SOPT2_TPMSRC(0x02)
102 )) | (uint32_t)(
103 SIM_SOPT2_TPMSRC(0x01)
104 )); /* Set the TPM clock */
105 /* Switch to FEI Mode */
106 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
107 MCG_C1 = MCG_C1_CLKS(0x00) |
108 MCG_C1_FRDIV(0x00) |
109 MCG_C1_IREFS_MASK |
110 MCG_C1_IRCLKEN_MASK;
111 /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
112 MCG_C2 &= (uint8_t)~(uint8_t)(
113 MCG_C2_LOCRE0_MASK |
114 MCG_C2_RANGE0(0x03) |
115 MCG_C2_HGO0_MASK |
116 MCG_C2_EREFS0_MASK |
117 MCG_C2_LP_MASK |
118 MCG_C2_IRCS_MASK
119 );
120 /* MCG_C4: DMX32=0,DRST_DRS=0 */
121 MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
122 /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
123 OSC0_CR = OSC_CR_ERCLKEN_MASK;
124 /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
125 MCG_C5 = MCG_C5_PRDIV0(0x00);
126 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
127 MCG_C6 = MCG_C6_VDIV0(0x00);
128 while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
129 }
130 while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
131 }
132
133 /*-- Update clock cfg --*/
134 DeviceClock.MCGIRCLKClockFreq = 32768;
135 DeviceClock.coreClockFreq = 20971520;
136 DeviceClock.platformClockFreq = 20971520;
137 DeviceClock.systemClockFreq = 20971520;
138 DeviceClock.busClockFreq = 20971520;
139 DeviceClock.flashClockFreq = 20971520;
140 DeviceClock.masterPeripheralClockFreq = 20971520>>1;
141 DeviceClock.OSCERCLKClockFreq = 0;
142 DeviceClock.ERCLK32KClockFreq = 1000;
143 DeviceClock.LowPowerOscillatorFreq = 1000;
144 DeviceClock.RtcClockOutFreq = 0;
145 }
tDeviceClock::coreClockFreq
unsigned long coreClockFreq
Definition: DSP_mkl16z256vlh4.h:347
tDeviceClock::MCGIRCLKClockFreq
unsigned long MCGIRCLKClockFreq
Definition: DSP_mkl16z256vlh4.h:346
tDeviceClock::LowPowerOscillatorFreq
unsigned long LowPowerOscillatorFreq
Definition: DSP_mkl16z256vlh4.h:355
tDeviceClock::OSCERCLKClockFreq
unsigned long OSCERCLKClockFreq
Definition: DSP_mkl16z256vlh4.h:353
tDeviceClock::platformClockFreq
unsigned long platformClockFreq
Definition: DSP_mkl16z256vlh4.h:348
DeviceClock
tDeviceClock DeviceClock
Definition: DSP_mkl16z256vlh4.c:53
tDeviceClock::flashClockFreq
unsigned long flashClockFreq
Definition: DSP_mkl16z256vlh4.h:351
tDeviceClock::masterPeripheralClockFreq
unsigned long masterPeripheralClockFreq
Definition: DSP_mkl16z256vlh4.h:352
tDeviceClock::systemClockFreq
unsigned long systemClockFreq
Definition: DSP_mkl16z256vlh4.h:349
tDeviceClock::RtcClockOutFreq
unsigned long RtcClockOutFreq
Definition: DSP_mkl16z256vlh4.h:356
tDeviceClock::ERCLK32KClockFreq
unsigned long ERCLK32KClockFreq
Definition: DSP_mkl16z256vlh4.h:354
tDeviceClock::busClockFreq
unsigned long busClockFreq
Definition: DSP_mkl16z256vlh4.h:350

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void DeviceClockSwitchHighPower | ( | void |  | ) |

Function to switch the processor on the highest clock speed allowed.

In this mode the processor is running with a 48MHz clock.

Definition at line 148 of file device.c.

References tDeviceClock::busClockFreq, tDeviceClock::coreClockFreq, DeviceClock, tDeviceClock::ERCLK32KClockFreq, tDeviceClock::flashClockFreq, tDeviceClock::LowPowerOscillatorFreq, tDeviceClock::masterPeripheralClockFreq, tDeviceClock::MCGIRCLKClockFreq, tDeviceClock::OSCERCLKClockFreq, tDeviceClock::platformClockFreq, tDeviceClock::RtcClockOutFreq, and tDeviceClock::systemClockFreq.

Referenced by CriticalInit(), and PowerManagerExitLPM().

148 {
149
150 /* System clock initialization */
151 /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
152 SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */
153 /* SIM_SCGC5: PORTC=1,PORTA=1 */
154 SIM_SCGC5 |= (SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
155 if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
156 /* PMC_REGSC: ACKISO=1 */
157 PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
158 }
159 /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
160 SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
161 /* SIM_SOPT2: PLLFLLSEL=1 */
162 SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
163 /* SIM_SOPT1: OSC32KSEL=2 */
164 SIM_SOPT1 = (uint32_t)((SIM_SOPT1 & (uint32_t)~(uint32_t)(
165 SIM_SOPT1_OSC32KSEL(0x01)
166 )) | (uint32_t)(
167 SIM_SOPT1_OSC32KSEL(0x02)
168 )); /* System oscillator drives 32 kHz clock for various peripherals */
169 /* SIM_SOPT2: TPMSRC=1 */
170 SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
171 SIM_SOPT2_TPMSRC(0x02)
172 )) | (uint32_t)(
173 SIM_SOPT2_TPMSRC(0x01)
174 )); /* Set the TPM clock */
175 /* PORTA_PCR18: ISF=0,MUX=0 */
176 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
177 /* PORTA_PCR19: ISF=0,MUX=0 */
178 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
179 /* Switch to FBE Mode */
180 /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
181 MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
182 MCG_C2_LOCRE0_MASK |
183 MCG_C2_RANGE0(0x01) |
184 MCG_C2_HGO0_MASK |
185 MCG_C2_LP_MASK |
186 MCG_C2_IRCS_MASK
187 )) | (uint8_t)(
188 MCG_C2_RANGE0(0x02) |
189 MCG_C2_EREFS0_MASK
190 ));
191 /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
192 OSC0_CR = OSC_CR_ERCLKEN_MASK;
193 /* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
194 MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
195 /* MCG_C4: DMX32=0,DRST_DRS=0 */
196 MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
197 /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=7 */
198 MCG_C5 = MCG_C5_PRDIV0(0x07);
199 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
200 MCG_C6 = MCG_C6_VDIV0(0x00);
201 while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
202 }
203 while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
204 }
205 /* Switch to PBE Mode */
206 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
207 MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));
208 while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
209 }
210 while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
211 }
212 /* Switch to PEE Mode */
213 /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
214 MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
215 while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
216 }
217 /* Initialization of the RTC_CLKIN pin */
218 /* PORTC_PCR1: ISF=0,MUX=1 */
219 PORTC_PCR1 = (uint32_t)((PORTC_PCR1 & (uint32_t)~(uint32_t)(
220 PORT_PCR_ISF_MASK |
221 PORT_PCR_MUX(0x06)
222 )) | (uint32_t)(
223 PORT_PCR_MUX(0x01)
224 ));
225
226 /*-- Update clock cfg --*/
227 DeviceClock.MCGIRCLKClockFreq = 32768;
228 DeviceClock.coreClockFreq = 48000000;
229 DeviceClock.platformClockFreq = 48000000;
230 DeviceClock.systemClockFreq = 48000000;
231 DeviceClock.busClockFreq = 24000000;
232 DeviceClock.flashClockFreq = 24000000;
233 DeviceClock.masterPeripheralClockFreq = 24000000;
234 DeviceClock.OSCERCLKClockFreq = 16000000;
235 DeviceClock.ERCLK32KClockFreq = 32768;
236 DeviceClock.LowPowerOscillatorFreq = 1000;
237 DeviceClock.RtcClockOutFreq = 0;
238 }
tDeviceClock::coreClockFreq
unsigned long coreClockFreq
Definition: DSP_mkl16z256vlh4.h:347
tDeviceClock::MCGIRCLKClockFreq
unsigned long MCGIRCLKClockFreq
Definition: DSP_mkl16z256vlh4.h:346
tDeviceClock::LowPowerOscillatorFreq
unsigned long LowPowerOscillatorFreq
Definition: DSP_mkl16z256vlh4.h:355
tDeviceClock::OSCERCLKClockFreq
unsigned long OSCERCLKClockFreq
Definition: DSP_mkl16z256vlh4.h:353
tDeviceClock::platformClockFreq
unsigned long platformClockFreq
Definition: DSP_mkl16z256vlh4.h:348
DeviceClock
tDeviceClock DeviceClock
Definition: DSP_mkl16z256vlh4.c:53
tDeviceClock::flashClockFreq
unsigned long flashClockFreq
Definition: DSP_mkl16z256vlh4.h:351
tDeviceClock::masterPeripheralClockFreq
unsigned long masterPeripheralClockFreq
Definition: DSP_mkl16z256vlh4.h:352
tDeviceClock::systemClockFreq
unsigned long systemClockFreq
Definition: DSP_mkl16z256vlh4.h:349
tDeviceClock::RtcClockOutFreq
unsigned long RtcClockOutFreq
Definition: DSP_mkl16z256vlh4.h:356
tDeviceClock::ERCLK32KClockFreq
unsigned long ERCLK32KClockFreq
Definition: DSP_mkl16z256vlh4.h:354
tDeviceClock::busClockFreq
unsigned long busClockFreq
Definition: DSP_mkl16z256vlh4.h:350

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void DeviceInit | ( | void |  | ) |

Function to initialize the device clock.

In this mode, processor is running with a 21MHz clock.

Definition at line 78 of file device.c.

References DeviceClockSwitchDefaultFEI().

Referenced by CriticalInit().

78 {
79
80 DeviceClockSwitchDefaultFEI();
81 }
DeviceClockSwitchDefaultFEI
void DeviceClockSwitchDefaultFEI(void)
Function to switch the processor clock on the FEI clock source.
Definition: device.c:84

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void LPM_DeepSleep | ( | void |  | ) |

Function to switch the device in deep sleep mode.

Definition at line 250 of file device.c.

References WakeFromInterrupt.

Referenced by LPM_VLPS().

250 {
251 /*=== Set the SLEEPDEEP bit to enable deep sleep mode (STOP) ===*/
252 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
253 WakeFromInterrupt(); //Enterring sleep
254 }
WakeFromInterrupt
#define WakeFromInterrupt()
Function used to enable the processor wakeUp from interrupt controller.
Definition: DSP_mkl16z256vlh4.h:441

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void LPM_Sleep | ( | void |  | ) |

Function to switch the device in sleep mode.

Definition at line 241 of file device.c.

References WakeFromInterrupt.

241 {
242 /* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep)
243 * mode instead of deep sleep.
244 */
245 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
246 WakeFromInterrupt();
247 }
WakeFromInterrupt
#define WakeFromInterrupt()
Function used to enable the processor wakeUp from interrupt controller.
Definition: DSP_mkl16z256vlh4.h:441

void LPM_VLPS | ( | void |  | ) |

Function to switch the device in very low power mode.

Definition at line 256 of file device.c.

References LPM_DeepSleep().

Referenced by PowerManagerEnterLPM().

256 {
257 volatile unsigned int dummyread;
258 /*The PMPROT register may have already been written by init
259 code. If so then this next write is not done since
260 PMPROT is write once after RESET.
261 This Write allows the MCU to enter the VLPR, VLPW,
262 and VLPS modes. If AVLP is already written to 0
263 Stop is entered instead of VLPS*/
264 SMC->PMPROT = SMC_PMPROT_AVLP_MASK;
265 /* Set the STOPM field to 0b010 for VLPS mode */
266 SMC->PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
267 SMC->PMCTRL |= SMC_PMCTRL_STOPM(0x2);
268 /*wait for write to complete to SMC before stopping core */
269 dummyread = SMC_PMCTRL;
270 /* Now execute the stop instruction to go into VLPS */
271 LPM_DeepSleep();
272 }
LPM_DeepSleep
void LPM_DeepSleep(void)
Function to switch the device in deep sleep mode.
Definition: device.c:250

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