   1              		.cpu cortex-m0plus
   2              		.fpu softvfp
   3              		.eabi_attribute 20, 1
   4              		.eabi_attribute 21, 1
   5              		.eabi_attribute 23, 3
   6              		.eabi_attribute 24, 1
   7              		.eabi_attribute 25, 1
   8              		.eabi_attribute 26, 1
   9              		.eabi_attribute 30, 6
  10              		.eabi_attribute 34, 0
  11              		.eabi_attribute 18, 4
  12              		.code	16
  13              		.file	"device.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.section	.text.DeviceInit,"ax",%progbits
  18              		.align	2
  19              		.global	DeviceInit
  20              		.code	16
  21              		.thumb_func
  23              	DeviceInit:
  24              	.LFB33:
  25              		.file 1 "../DSP/Device/device.c"
   1:../DSP/Device/device.c **** /*############################################################################################*/
   2:../DSP/Device/device.c **** /*############################################################################################*/
   3:../DSP/Device/device.c **** /**
   4:../DSP/Device/device.c ****  * \file    device.c
   5:../DSP/Device/device.c ****  * \author  Thibaut LALUQUE 3D-Ouest
   6:../DSP/Device/device.c ****  * \date    26/09/2014
   7:../DSP/Device/device.c ****  * \version 1.0
   8:../DSP/Device/device.c ****  * \brief Source file for low level initialization and specific device feature.
   9:../DSP/Device/device.c ****  * \details All Right Reserved.
  10:../DSP/Device/device.c ****  */
  11:../DSP/Device/device.c **** /*############################################################################################*/
  12:../DSP/Device/device.c **** /*############################################################################################*/
  13:../DSP/Device/device.c **** 
  14:../DSP/Device/device.c **** 
  15:../DSP/Device/device.c **** /*############################################################################################*/
  16:../DSP/Device/device.c **** /*## INCLUDES ################################################################################*/
  17:../DSP/Device/device.c **** /*############################################################################################*/
  18:../DSP/Device/device.c **** #include "device.h"
  19:../DSP/Device/device.c **** /*############################################################################################*/
  20:../DSP/Device/device.c **** /*## END INCLUDES ############################################################################*/
  21:../DSP/Device/device.c **** /*############################################################################################*/
  22:../DSP/Device/device.c **** 
  23:../DSP/Device/device.c **** /*############################################################################################*/
  24:../DSP/Device/device.c **** /*## CONFIGURATION BITS ######################################################################*/
  25:../DSP/Device/device.c **** /*############################################################################################*/
  26:../DSP/Device/device.c **** 
  27:../DSP/Device/device.c **** /*############################################################################################*/
  28:../DSP/Device/device.c **** /*## END CONFIGURATION BITS ##################################################################*/
  29:../DSP/Device/device.c **** /*############################################################################################*/
  30:../DSP/Device/device.c **** 
  31:../DSP/Device/device.c **** /*############################################################################################*/
  32:../DSP/Device/device.c **** /*## LOCAL DEFINES ###########################################################################*/
  33:../DSP/Device/device.c **** /*############################################################################################*/
  34:../DSP/Device/device.c **** 
  35:../DSP/Device/device.c **** /*############################################################################################*/
  36:../DSP/Device/device.c **** /*## END LOCAL DEFINES ######################################################################*/
  37:../DSP/Device/device.c **** /*############################################################################################*/
  38:../DSP/Device/device.c **** 
  39:../DSP/Device/device.c **** 
  40:../DSP/Device/device.c **** /*############################################################################################*/
  41:../DSP/Device/device.c **** /*## LOCAL FONCTIONS DECLARATION #############################################################*/
  42:../DSP/Device/device.c **** /*############################################################################################*/
  43:../DSP/Device/device.c **** 
  44:../DSP/Device/device.c **** /*############################################################################################*/
  45:../DSP/Device/device.c **** /*## END LOCAL FONCTIONS DECLARATION #########################################################*/
  46:../DSP/Device/device.c **** /*############################################################################################*/
  47:../DSP/Device/device.c **** 
  48:../DSP/Device/device.c **** 
  49:../DSP/Device/device.c **** /*############################################################################################*/
  50:../DSP/Device/device.c **** /*## LOCAL VARIABLES #########################################################################*/
  51:../DSP/Device/device.c **** /*############################################################################################*/
  52:../DSP/Device/device.c **** 
  53:../DSP/Device/device.c **** /*############################################################################################*/
  54:../DSP/Device/device.c **** /*## END LOCAL VARIABLES #####################################################################*/
  55:../DSP/Device/device.c **** /*############################################################################################*/
  56:../DSP/Device/device.c **** 
  57:../DSP/Device/device.c **** /*############################################################################################*/
  58:../DSP/Device/device.c **** /*## GLOBAL VARIABLES ########################################################################*/
  59:../DSP/Device/device.c **** /*############################################################################################*/
  60:../DSP/Device/device.c **** 
  61:../DSP/Device/device.c **** /*############################################################################################*/
  62:../DSP/Device/device.c **** /*## END GLOBAL VARIABLES ####################################################################*/
  63:../DSP/Device/device.c **** /*############################################################################################*/
  64:../DSP/Device/device.c **** 
  65:../DSP/Device/device.c **** 
  66:../DSP/Device/device.c **** /*############################################################################################*/
  67:../DSP/Device/device.c **** /*## LOCAL FONCTIONS #########################################################################*/
  68:../DSP/Device/device.c **** /*############################################################################################*/
  69:../DSP/Device/device.c **** 
  70:../DSP/Device/device.c **** /*############################################################################################*/
  71:../DSP/Device/device.c **** /*## END LOCAL FONCTIONS #####################################################################*/
  72:../DSP/Device/device.c **** /*############################################################################################*/
  73:../DSP/Device/device.c **** 
  74:../DSP/Device/device.c **** 
  75:../DSP/Device/device.c **** /*############################################################################################*/
  76:../DSP/Device/device.c **** /*## EXTERNAL FONCTIONS ######################################################################*/
  77:../DSP/Device/device.c **** /*############################################################################################*/
  78:../DSP/Device/device.c **** void DeviceInit (void) {
  26              		.loc 1 78 0
  27              		.cfi_startproc
  28 0000 80B5     		push	{r7, lr}
  29              		.cfi_def_cfa_offset 8
  30              		.cfi_offset 7, -8
  31              		.cfi_offset 14, -4
  32 0002 00AF     		add	r7, sp, #0
  33              		.cfi_def_cfa_register 7
  79:../DSP/Device/device.c **** 
  80:../DSP/Device/device.c **** 	DeviceClockSwitchDefaultFEI();
  34              		.loc 1 80 0
  35 0004 FFF7FEFF 		bl	DeviceClockSwitchDefaultFEI
  81:../DSP/Device/device.c **** }
  36              		.loc 1 81 0
  37 0008 BD46     		mov	sp, r7
  38              		@ sp needed
  39 000a 80BD     		pop	{r7, pc}
  40              		.cfi_endproc
  41              	.LFE33:
  43              		.section	.text.DeviceClockSwitchDefaultFEI,"ax",%progbits
  44              		.align	2
  45              		.global	DeviceClockSwitchDefaultFEI
  46              		.code	16
  47              		.thumb_func
  49              	DeviceClockSwitchDefaultFEI:
  50              	.LFB34:
  82:../DSP/Device/device.c **** 
  83:../DSP/Device/device.c **** 
  84:../DSP/Device/device.c **** void DeviceClockSwitchDefaultFEI (void) {
  51              		.loc 1 84 0
  52              		.cfi_startproc
  53 0000 80B5     		push	{r7, lr}
  54              		.cfi_def_cfa_offset 8
  55              		.cfi_offset 7, -8
  56              		.cfi_offset 14, -4
  57 0002 00AF     		add	r7, sp, #0
  58              		.cfi_def_cfa_register 7
  85:../DSP/Device/device.c **** 
  86:../DSP/Device/device.c **** 	/*===Set oscillator to safe value ===*/
  87:../DSP/Device/device.c **** 	SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescaler
  59              		.loc 1 87 0
  60 0004 494A     		ldr	r2, .L6
  61 0006 4A4B     		ldr	r3, .L6+4
  62 0008 C021     		mov	r1, #192
  63 000a 8902     		lsl	r1, r1, #10
  64 000c D150     		str	r1, [r2, r3]
  88:../DSP/Device/device.c **** 	SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
  65              		.loc 1 88 0
  66 000e 474A     		ldr	r2, .L6
  67 0010 4649     		ldr	r1, .L6
  68 0012 484B     		ldr	r3, .L6+8
  69 0014 CB58     		ldr	r3, [r1, r3]
  70 0016 8021     		mov	r1, #128
  71 0018 8900     		lsl	r1, r1, #2
  72 001a 1943     		orr	r1, r3
  73 001c 454B     		ldr	r3, .L6+8
  74 001e D150     		str	r1, [r2, r3]
  89:../DSP/Device/device.c **** 	if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
  75              		.loc 1 89 0
  76 0020 454B     		ldr	r3, .L6+12
  77 0022 9B78     		ldrb	r3, [r3, #2]
  78 0024 DBB2     		uxtb	r3, r3
  79 0026 1A1C     		mov	r2, r3
  80 0028 0823     		mov	r3, #8
  81 002a 1340     		and	r3, r2
  82 002c 07D0     		beq	.L3
  90:../DSP/Device/device.c **** 		PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
  83              		.loc 1 90 0
  84 002e 424B     		ldr	r3, .L6+12
  85 0030 414A     		ldr	r2, .L6+12
  86 0032 9278     		ldrb	r2, [r2, #2]
  87 0034 D2B2     		uxtb	r2, r2
  88 0036 0821     		mov	r1, #8
  89 0038 0A43     		orr	r2, r1
  90 003a D2B2     		uxtb	r2, r2
  91 003c 9A70     		strb	r2, [r3, #2]
  92              	.L3:
  91:../DSP/Device/device.c **** 	}
  92:../DSP/Device/device.c **** 
  93:../DSP/Device/device.c **** 	/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??
  94:../DSP/Device/device.c **** 	SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers
  93              		.loc 1 94 0
  94 003e 3B4A     		ldr	r2, .L6
  95 0040 3B4B     		ldr	r3, .L6+4
  96 0042 0021     		mov	r1, #0
  97 0044 D150     		str	r1, [r2, r3]
  95:../DSP/Device/device.c **** 	/* SIM_SOPT2: PLLFLLSEL=0 */
  96:../DSP/Device/device.c **** 	SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for 
  98              		.loc 1 96 0
  99 0046 394A     		ldr	r2, .L6
 100 0048 3849     		ldr	r1, .L6
 101 004a 3C4B     		ldr	r3, .L6+16
 102 004c C958     		ldr	r1, [r1, r3]
 103 004e 3C4B     		ldr	r3, .L6+20
 104 0050 1940     		and	r1, r3
 105 0052 3A4B     		ldr	r3, .L6+16
 106 0054 D150     		str	r1, [r2, r3]
  97:../DSP/Device/device.c **** 	/* SIM_SOPT1: OSC32KSEL=3 */
  98:../DSP/Device/device.c **** 	SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various per
 107              		.loc 1 98 0
 108 0056 354B     		ldr	r3, .L6
 109 0058 344A     		ldr	r2, .L6
 110 005a 1268     		ldr	r2, [r2]
 111 005c C021     		mov	r1, #192
 112 005e 0903     		lsl	r1, r1, #12
 113 0060 0A43     		orr	r2, r1
 114 0062 1A60     		str	r2, [r3]
  99:../DSP/Device/device.c **** 	/* SIM_SOPT2: TPMSRC=1 */
 100:../DSP/Device/device.c **** 	SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
 115              		.loc 1 100 0
 116 0064 314A     		ldr	r2, .L6
 117 0066 3149     		ldr	r1, .L6
 118 0068 344B     		ldr	r3, .L6+16
 119 006a C958     		ldr	r1, [r1, r3]
 120 006c 354B     		ldr	r3, .L6+24
 121 006e 0B40     		and	r3, r1
 122 0070 8021     		mov	r1, #128
 123 0072 4904     		lsl	r1, r1, #17
 124 0074 1943     		orr	r1, r3
 125 0076 314B     		ldr	r3, .L6+16
 126 0078 D150     		str	r1, [r2, r3]
 101:../DSP/Device/device.c **** 			SIM_SOPT2_TPMSRC(0x02)
 102:../DSP/Device/device.c **** 	)) | (uint32_t)(
 103:../DSP/Device/device.c **** 			SIM_SOPT2_TPMSRC(0x01)
 104:../DSP/Device/device.c **** 	));                      /* Set the TPM clock */
 105:../DSP/Device/device.c **** 	/* Switch to FEI Mode */
 106:../DSP/Device/device.c **** 	/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 107:../DSP/Device/device.c **** 	MCG_C1 = MCG_C1_CLKS(0x00) |
 127              		.loc 1 107 0
 128 007a 334B     		ldr	r3, .L6+28
 129 007c 0622     		mov	r2, #6
 130 007e 1A70     		strb	r2, [r3]
 108:../DSP/Device/device.c **** 			MCG_C1_FRDIV(0x00) |
 109:../DSP/Device/device.c **** 			MCG_C1_IREFS_MASK |
 110:../DSP/Device/device.c **** 			MCG_C1_IRCLKEN_MASK;
 111:../DSP/Device/device.c **** 	/* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
 112:../DSP/Device/device.c **** 	MCG_C2 &= (uint8_t)~(uint8_t)(
 131              		.loc 1 112 0
 132 0080 314B     		ldr	r3, .L6+28
 133 0082 314A     		ldr	r2, .L6+28
 134 0084 5278     		ldrb	r2, [r2, #1]
 135 0086 D1B2     		uxtb	r1, r2
 136 0088 4022     		mov	r2, #64
 137 008a 0A40     		and	r2, r1
 138 008c D2B2     		uxtb	r2, r2
 139 008e 5A70     		strb	r2, [r3, #1]
 113:../DSP/Device/device.c **** 			MCG_C2_LOCRE0_MASK |
 114:../DSP/Device/device.c **** 			MCG_C2_RANGE0(0x03) |
 115:../DSP/Device/device.c **** 			MCG_C2_HGO0_MASK |
 116:../DSP/Device/device.c **** 			MCG_C2_EREFS0_MASK |
 117:../DSP/Device/device.c **** 			MCG_C2_LP_MASK |
 118:../DSP/Device/device.c **** 			MCG_C2_IRCS_MASK
 119:../DSP/Device/device.c **** 	);
 120:../DSP/Device/device.c **** 	/* MCG_C4: DMX32=0,DRST_DRS=0 */
 121:../DSP/Device/device.c **** 	MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
 140              		.loc 1 121 0
 141 0090 2D4B     		ldr	r3, .L6+28
 142 0092 2D4A     		ldr	r2, .L6+28
 143 0094 D278     		ldrb	r2, [r2, #3]
 144 0096 D1B2     		uxtb	r1, r2
 145 0098 1F22     		mov	r2, #31
 146 009a 0A40     		and	r2, r1
 147 009c D2B2     		uxtb	r2, r2
 148 009e DA70     		strb	r2, [r3, #3]
 122:../DSP/Device/device.c **** 	/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 123:../DSP/Device/device.c **** 	OSC0_CR = OSC_CR_ERCLKEN_MASK;
 149              		.loc 1 123 0
 150 00a0 2A4B     		ldr	r3, .L6+32
 151 00a2 8022     		mov	r2, #128
 152 00a4 1A70     		strb	r2, [r3]
 124:../DSP/Device/device.c **** 	/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 125:../DSP/Device/device.c **** 	MCG_C5 = MCG_C5_PRDIV0(0x00);
 153              		.loc 1 125 0
 154 00a6 284B     		ldr	r3, .L6+28
 155 00a8 0022     		mov	r2, #0
 156 00aa 1A71     		strb	r2, [r3, #4]
 126:../DSP/Device/device.c **** 	/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 127:../DSP/Device/device.c **** 	MCG_C6 = MCG_C6_VDIV0(0x00);
 157              		.loc 1 127 0
 158 00ac 264B     		ldr	r3, .L6+28
 159 00ae 0022     		mov	r2, #0
 160 00b0 5A71     		strb	r2, [r3, #5]
 128:../DSP/Device/device.c **** 	while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock 
 161              		.loc 1 128 0
 162 00b2 C046     		mov	r8, r8
 163              	.L4:
 164              		.loc 1 128 0 is_stmt 0 discriminator 1
 165 00b4 244B     		ldr	r3, .L6+28
 166 00b6 9B79     		ldrb	r3, [r3, #6]
 167 00b8 DBB2     		uxtb	r3, r3
 168 00ba 1A1C     		mov	r2, r3
 169 00bc 1023     		mov	r3, #16
 170 00be 1340     		and	r3, r2
 171 00c0 F8D0     		beq	.L4
 129:../DSP/Device/device.c **** 	}
 130:../DSP/Device/device.c **** 	while((MCG_S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
 172              		.loc 1 130 0 is_stmt 1
 173 00c2 C046     		mov	r8, r8
 174              	.L5:
 175              		.loc 1 130 0 is_stmt 0 discriminator 1
 176 00c4 204B     		ldr	r3, .L6+28
 177 00c6 9B79     		ldrb	r3, [r3, #6]
 178 00c8 DBB2     		uxtb	r3, r3
 179 00ca 1A1C     		mov	r2, r3
 180 00cc 0C23     		mov	r3, #12
 181 00ce 1340     		and	r3, r2
 182 00d0 F8D1     		bne	.L5
 131:../DSP/Device/device.c **** 	}
 132:../DSP/Device/device.c **** 
 133:../DSP/Device/device.c **** 	/*-- Update clock cfg --*/
 134:../DSP/Device/device.c **** 	DeviceClock.MCGIRCLKClockFreq = 32768;
 183              		.loc 1 134 0 is_stmt 1
 184 00d2 1F4B     		ldr	r3, .L6+36
 185 00d4 8022     		mov	r2, #128
 186 00d6 1202     		lsl	r2, r2, #8
 187 00d8 1A60     		str	r2, [r3]
 135:../DSP/Device/device.c **** 	DeviceClock.coreClockFreq = 20971520;
 188              		.loc 1 135 0
 189 00da 1D4B     		ldr	r3, .L6+36
 190 00dc A022     		mov	r2, #160
 191 00de 5204     		lsl	r2, r2, #17
 192 00e0 5A60     		str	r2, [r3, #4]
 136:../DSP/Device/device.c **** 	DeviceClock.platformClockFreq = 20971520;
 193              		.loc 1 136 0
 194 00e2 1B4B     		ldr	r3, .L6+36
 195 00e4 A022     		mov	r2, #160
 196 00e6 5204     		lsl	r2, r2, #17
 197 00e8 9A60     		str	r2, [r3, #8]
 137:../DSP/Device/device.c **** 	DeviceClock.systemClockFreq = 20971520;
 198              		.loc 1 137 0
 199 00ea 194B     		ldr	r3, .L6+36
 200 00ec A022     		mov	r2, #160
 201 00ee 5204     		lsl	r2, r2, #17
 202 00f0 DA60     		str	r2, [r3, #12]
 138:../DSP/Device/device.c **** 	DeviceClock.busClockFreq = 20971520;
 203              		.loc 1 138 0
 204 00f2 174B     		ldr	r3, .L6+36
 205 00f4 A022     		mov	r2, #160
 206 00f6 5204     		lsl	r2, r2, #17
 207 00f8 1A61     		str	r2, [r3, #16]
 139:../DSP/Device/device.c **** 	DeviceClock.flashClockFreq = 20971520;
 208              		.loc 1 139 0
 209 00fa 154B     		ldr	r3, .L6+36
 210 00fc A022     		mov	r2, #160
 211 00fe 5204     		lsl	r2, r2, #17
 212 0100 5A61     		str	r2, [r3, #20]
 140:../DSP/Device/device.c **** 	DeviceClock.masterPeripheralClockFreq = 20971520>>1;
 213              		.loc 1 140 0
 214 0102 134B     		ldr	r3, .L6+36
 215 0104 A022     		mov	r2, #160
 216 0106 1204     		lsl	r2, r2, #16
 217 0108 9A61     		str	r2, [r3, #24]
 141:../DSP/Device/device.c **** 	DeviceClock.OSCERCLKClockFreq = 0;
 218              		.loc 1 141 0
 219 010a 114B     		ldr	r3, .L6+36
 220 010c 0022     		mov	r2, #0
 221 010e DA61     		str	r2, [r3, #28]
 142:../DSP/Device/device.c **** 	DeviceClock.ERCLK32KClockFreq = 1000;
 222              		.loc 1 142 0
 223 0110 0F4B     		ldr	r3, .L6+36
 224 0112 FA22     		mov	r2, #250
 225 0114 9200     		lsl	r2, r2, #2
 226 0116 1A62     		str	r2, [r3, #32]
 143:../DSP/Device/device.c **** 	DeviceClock.LowPowerOscillatorFreq = 1000;
 227              		.loc 1 143 0
 228 0118 0D4B     		ldr	r3, .L6+36
 229 011a FA22     		mov	r2, #250
 230 011c 9200     		lsl	r2, r2, #2
 231 011e 5A62     		str	r2, [r3, #36]
 144:../DSP/Device/device.c **** 	DeviceClock.RtcClockOutFreq = 0;
 232              		.loc 1 144 0
 233 0120 0B4B     		ldr	r3, .L6+36
 234 0122 0022     		mov	r2, #0
 235 0124 9A62     		str	r2, [r3, #40]
 145:../DSP/Device/device.c **** }
 236              		.loc 1 145 0
 237 0126 BD46     		mov	sp, r7
 238              		@ sp needed
 239 0128 80BD     		pop	{r7, pc}
 240              	.L7:
 241 012a C046     		.align	2
 242              	.L6:
 243 012c 00700440 		.word	1074032640
 244 0130 44100000 		.word	4164
 245 0134 38100000 		.word	4152
 246 0138 00D00740 		.word	1074253824
 247 013c 04100000 		.word	4100
 248 0140 FFFFFEFF 		.word	-65537
 249 0144 FFFFFFFC 		.word	-50331649
 250 0148 00400640 		.word	1074151424
 251 014c 00500640 		.word	1074155520
 252 0150 00000000 		.word	DeviceClock
 253              		.cfi_endproc
 254              	.LFE34:
 256              		.section	.text.DeviceClockSwitchHighPower,"ax",%progbits
 257              		.align	2
 258              		.global	DeviceClockSwitchHighPower
 259              		.code	16
 260              		.thumb_func
 262              	DeviceClockSwitchHighPower:
 263              	.LFB35:
 146:../DSP/Device/device.c **** 
 147:../DSP/Device/device.c **** 
 148:../DSP/Device/device.c **** void DeviceClockSwitchHighPower (void) {
 264              		.loc 1 148 0
 265              		.cfi_startproc
 266 0000 80B5     		push	{r7, lr}
 267              		.cfi_def_cfa_offset 8
 268              		.cfi_offset 7, -8
 269              		.cfi_offset 14, -4
 270 0002 00AF     		add	r7, sp, #0
 271              		.cfi_def_cfa_register 7
 149:../DSP/Device/device.c **** 
 150:../DSP/Device/device.c **** 	/* System clock initialization */
 151:../DSP/Device/device.c **** 	  /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,
 152:../DSP/Device/device.c **** 	  SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescal
 272              		.loc 1 152 0
 273 0004 664A     		ldr	r2, .L15
 274 0006 674B     		ldr	r3, .L15+4
 275 0008 C021     		mov	r1, #192
 276 000a 8902     		lsl	r1, r1, #10
 277 000c D150     		str	r1, [r2, r3]
 153:../DSP/Device/device.c **** 	  /* SIM_SCGC5: PORTC=1,PORTA=1 */
 154:../DSP/Device/device.c **** 	  SIM_SCGC5 |= (SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to en
 278              		.loc 1 154 0
 279 000e 644A     		ldr	r2, .L15
 280 0010 6349     		ldr	r1, .L15
 281 0012 654B     		ldr	r3, .L15+8
 282 0014 CB58     		ldr	r3, [r1, r3]
 283 0016 A021     		mov	r1, #160
 284 0018 0901     		lsl	r1, r1, #4
 285 001a 1943     		orr	r1, r3
 286 001c 624B     		ldr	r3, .L15+8
 287 001e D150     		str	r1, [r2, r3]
 155:../DSP/Device/device.c **** 	  if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
 288              		.loc 1 155 0
 289 0020 624B     		ldr	r3, .L15+12
 290 0022 9B78     		ldrb	r3, [r3, #2]
 291 0024 DBB2     		uxtb	r3, r3
 292 0026 1A1C     		mov	r2, r3
 293 0028 0823     		mov	r3, #8
 294 002a 1340     		and	r3, r2
 295 002c 07D0     		beq	.L9
 156:../DSP/Device/device.c **** 	    /* PMC_REGSC: ACKISO=1 */
 157:../DSP/Device/device.c **** 	    PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
 296              		.loc 1 157 0
 297 002e 5F4B     		ldr	r3, .L15+12
 298 0030 5E4A     		ldr	r2, .L15+12
 299 0032 9278     		ldrb	r2, [r2, #2]
 300 0034 D2B2     		uxtb	r2, r2
 301 0036 0821     		mov	r1, #8
 302 0038 0A43     		orr	r2, r1
 303 003a D2B2     		uxtb	r2, r2
 304 003c 9A70     		strb	r2, [r3, #2]
 305              	.L9:
 158:../DSP/Device/device.c **** 	  }
 159:../DSP/Device/device.c **** 	  /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,
 160:../DSP/Device/device.c **** 	  SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescale
 306              		.loc 1 160 0
 307 003e 584A     		ldr	r2, .L15
 308 0040 584B     		ldr	r3, .L15+4
 309 0042 8021     		mov	r1, #128
 310 0044 4902     		lsl	r1, r1, #9
 311 0046 D150     		str	r1, [r2, r3]
 161:../DSP/Device/device.c **** 	  /* SIM_SOPT2: PLLFLLSEL=1 */
 162:../DSP/Device/device.c **** 	  SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals *
 312              		.loc 1 162 0
 313 0048 554A     		ldr	r2, .L15
 314 004a 5549     		ldr	r1, .L15
 315 004c 584B     		ldr	r3, .L15+16
 316 004e CB58     		ldr	r3, [r1, r3]
 317 0050 8021     		mov	r1, #128
 318 0052 4902     		lsl	r1, r1, #9
 319 0054 1943     		orr	r1, r3
 320 0056 564B     		ldr	r3, .L15+16
 321 0058 D150     		str	r1, [r2, r3]
 163:../DSP/Device/device.c **** 	  /* SIM_SOPT1: OSC32KSEL=2 */
 164:../DSP/Device/device.c **** 	  SIM_SOPT1 = (uint32_t)((SIM_SOPT1 & (uint32_t)~(uint32_t)(
 322              		.loc 1 164 0
 323 005a 514B     		ldr	r3, .L15
 324 005c 504A     		ldr	r2, .L15
 325 005e 1168     		ldr	r1, [r2]
 326 0060 544A     		ldr	r2, .L15+20
 327 0062 0A40     		and	r2, r1
 328 0064 8021     		mov	r1, #128
 329 0066 0903     		lsl	r1, r1, #12
 330 0068 0A43     		orr	r2, r1
 331 006a 1A60     		str	r2, [r3]
 165:../DSP/Device/device.c **** 	               SIM_SOPT1_OSC32KSEL(0x01)
 166:../DSP/Device/device.c **** 	              )) | (uint32_t)(
 167:../DSP/Device/device.c **** 	               SIM_SOPT1_OSC32KSEL(0x02)
 168:../DSP/Device/device.c **** 	              ));                      /* System oscillator drives 32 kHz clock for various periph
 169:../DSP/Device/device.c **** 	  /* SIM_SOPT2: TPMSRC=1 */
 170:../DSP/Device/device.c **** 	  SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
 332              		.loc 1 170 0
 333 006c 4C4A     		ldr	r2, .L15
 334 006e 4C49     		ldr	r1, .L15
 335 0070 4F4B     		ldr	r3, .L15+16
 336 0072 C958     		ldr	r1, [r1, r3]
 337 0074 504B     		ldr	r3, .L15+24
 338 0076 0B40     		and	r3, r1
 339 0078 8021     		mov	r1, #128
 340 007a 4904     		lsl	r1, r1, #17
 341 007c 1943     		orr	r1, r3
 342 007e 4C4B     		ldr	r3, .L15+16
 343 0080 D150     		str	r1, [r2, r3]
 171:../DSP/Device/device.c **** 	               SIM_SOPT2_TPMSRC(0x02)
 172:../DSP/Device/device.c **** 	              )) | (uint32_t)(
 173:../DSP/Device/device.c **** 	               SIM_SOPT2_TPMSRC(0x01)
 174:../DSP/Device/device.c **** 	              ));                      /* Set the TPM clock */
 175:../DSP/Device/device.c **** 	  /* PORTA_PCR18: ISF=0,MUX=0 */
 176:../DSP/Device/device.c **** 	  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 344              		.loc 1 176 0
 345 0082 4E4B     		ldr	r3, .L15+28
 346 0084 4D4A     		ldr	r2, .L15+28
 347 0086 916C     		ldr	r1, [r2, #72]
 348 0088 4D4A     		ldr	r2, .L15+32
 349 008a 0A40     		and	r2, r1
 350 008c 9A64     		str	r2, [r3, #72]
 177:../DSP/Device/device.c **** 	  /* PORTA_PCR19: ISF=0,MUX=0 */
 178:../DSP/Device/device.c **** 	  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 351              		.loc 1 178 0
 352 008e 4B4B     		ldr	r3, .L15+28
 353 0090 4A4A     		ldr	r2, .L15+28
 354 0092 D16C     		ldr	r1, [r2, #76]
 355 0094 4A4A     		ldr	r2, .L15+32
 356 0096 0A40     		and	r2, r1
 357 0098 DA64     		str	r2, [r3, #76]
 179:../DSP/Device/device.c **** 	  /* Switch to FBE Mode */
 180:../DSP/Device/device.c **** 	  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
 181:../DSP/Device/device.c **** 	  MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
 358              		.loc 1 181 0
 359 009a 4A4B     		ldr	r3, .L15+36
 360 009c 494A     		ldr	r2, .L15+36
 361 009e 5278     		ldrb	r2, [r2, #1]
 362 00a0 D2B2     		uxtb	r2, r2
 363 00a2 D2B2     		uxtb	r2, r2
 364 00a4 111C     		add	r1, r2, #0
 365 00a6 4022     		mov	r2, #64
 366 00a8 0A40     		and	r2, r1
 367 00aa D2B2     		uxtb	r2, r2
 368 00ac 2421     		mov	r1, #36
 369 00ae 0A43     		orr	r2, r1
 370 00b0 D2B2     		uxtb	r2, r2
 371 00b2 D2B2     		uxtb	r2, r2
 372 00b4 5A70     		strb	r2, [r3, #1]
 182:../DSP/Device/device.c **** 	            MCG_C2_LOCRE0_MASK |
 183:../DSP/Device/device.c **** 	            MCG_C2_RANGE0(0x01) |
 184:../DSP/Device/device.c **** 	            MCG_C2_HGO0_MASK |
 185:../DSP/Device/device.c **** 	            MCG_C2_LP_MASK |
 186:../DSP/Device/device.c **** 	            MCG_C2_IRCS_MASK
 187:../DSP/Device/device.c **** 	           )) | (uint8_t)(
 188:../DSP/Device/device.c **** 	            MCG_C2_RANGE0(0x02) |
 189:../DSP/Device/device.c **** 	            MCG_C2_EREFS0_MASK
 190:../DSP/Device/device.c **** 	           ));
 191:../DSP/Device/device.c **** 	  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 192:../DSP/Device/device.c **** 	  OSC0_CR = OSC_CR_ERCLKEN_MASK;
 373              		.loc 1 192 0
 374 00b6 444B     		ldr	r3, .L15+40
 375 00b8 8022     		mov	r2, #128
 376 00ba 1A70     		strb	r2, [r3]
 193:../DSP/Device/device.c **** 	  /* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 194:../DSP/Device/device.c **** 	  MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
 377              		.loc 1 194 0
 378 00bc 414B     		ldr	r3, .L15+36
 379 00be A222     		mov	r2, #162
 380 00c0 1A70     		strb	r2, [r3]
 195:../DSP/Device/device.c **** 	  /* MCG_C4: DMX32=0,DRST_DRS=0 */
 196:../DSP/Device/device.c **** 	  MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
 381              		.loc 1 196 0
 382 00c2 404B     		ldr	r3, .L15+36
 383 00c4 3F4A     		ldr	r2, .L15+36
 384 00c6 D278     		ldrb	r2, [r2, #3]
 385 00c8 D1B2     		uxtb	r1, r2
 386 00ca 1F22     		mov	r2, #31
 387 00cc 0A40     		and	r2, r1
 388 00ce D2B2     		uxtb	r2, r2
 389 00d0 DA70     		strb	r2, [r3, #3]
 197:../DSP/Device/device.c **** 	  /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=7 */
 198:../DSP/Device/device.c **** 	  MCG_C5 = MCG_C5_PRDIV0(0x07);
 390              		.loc 1 198 0
 391 00d2 3C4B     		ldr	r3, .L15+36
 392 00d4 0722     		mov	r2, #7
 393 00d6 1A71     		strb	r2, [r3, #4]
 199:../DSP/Device/device.c **** 	  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 200:../DSP/Device/device.c **** 	  MCG_C6 = MCG_C6_VDIV0(0x00);
 394              		.loc 1 200 0
 395 00d8 3A4B     		ldr	r3, .L15+36
 396 00da 0022     		mov	r2, #0
 397 00dc 5A71     		strb	r2, [r3, #5]
 201:../DSP/Device/device.c **** 	  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference cloc
 398              		.loc 1 201 0
 399 00de C046     		mov	r8, r8
 400              	.L10:
 401              		.loc 1 201 0 is_stmt 0 discriminator 1
 402 00e0 384B     		ldr	r3, .L15+36
 403 00e2 9B79     		ldrb	r3, [r3, #6]
 404 00e4 DBB2     		uxtb	r3, r3
 405 00e6 1A1C     		mov	r2, r3
 406 00e8 1023     		mov	r3, #16
 407 00ea 1340     		and	r3, r2
 408 00ec F8D1     		bne	.L10
 202:../DSP/Device/device.c **** 	  }
 203:../DSP/Device/device.c **** 	  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG o
 409              		.loc 1 203 0 is_stmt 1
 410 00ee C046     		mov	r8, r8
 411              	.L11:
 412              		.loc 1 203 0 is_stmt 0 discriminator 1
 413 00f0 344B     		ldr	r3, .L15+36
 414 00f2 9B79     		ldrb	r3, [r3, #6]
 415 00f4 DBB2     		uxtb	r3, r3
 416 00f6 1A1C     		mov	r2, r3
 417 00f8 0C23     		mov	r3, #12
 418 00fa 1340     		and	r3, r2
 419 00fc 082B     		cmp	r3, #8
 420 00fe F7D1     		bne	.L11
 204:../DSP/Device/device.c **** 	  }
 205:../DSP/Device/device.c **** 	  /* Switch to PBE Mode */
 206:../DSP/Device/device.c **** 	  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
 207:../DSP/Device/device.c **** 	  MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));
 421              		.loc 1 207 0 is_stmt 1
 422 0100 304B     		ldr	r3, .L15+36
 423 0102 4022     		mov	r2, #64
 424 0104 5A71     		strb	r2, [r3, #5]
 208:../DSP/Device/device.c **** 	  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG o
 425              		.loc 1 208 0
 426 0106 C046     		mov	r8, r8
 427              	.L12:
 428              		.loc 1 208 0 is_stmt 0 discriminator 1
 429 0108 2E4B     		ldr	r3, .L15+36
 430 010a 9B79     		ldrb	r3, [r3, #6]
 431 010c DBB2     		uxtb	r3, r3
 432 010e 1A1C     		mov	r2, r3
 433 0110 0C23     		mov	r3, #12
 434 0112 1340     		and	r3, r2
 435 0114 082B     		cmp	r3, #8
 436 0116 F7D1     		bne	.L12
 209:../DSP/Device/device.c **** 	  }
 210:../DSP/Device/device.c **** 	  while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
 437              		.loc 1 210 0 is_stmt 1
 438 0118 C046     		mov	r8, r8
 439              	.L13:
 440              		.loc 1 210 0 is_stmt 0 discriminator 1
 441 011a 2A4B     		ldr	r3, .L15+36
 442 011c 9B79     		ldrb	r3, [r3, #6]
 443 011e DBB2     		uxtb	r3, r3
 444 0120 1A1C     		mov	r2, r3
 445 0122 4023     		mov	r3, #64
 446 0124 1340     		and	r3, r2
 447 0126 F8D0     		beq	.L13
 211:../DSP/Device/device.c **** 	  }
 212:../DSP/Device/device.c **** 	  /* Switch to PEE Mode */
 213:../DSP/Device/device.c **** 	  /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 214:../DSP/Device/device.c **** 	  MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
 448              		.loc 1 214 0 is_stmt 1
 449 0128 264B     		ldr	r3, .L15+36
 450 012a 2222     		mov	r2, #34
 451 012c 1A70     		strb	r2, [r3]
 215:../DSP/Device/device.c **** 	  while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
 452              		.loc 1 215 0
 453 012e C046     		mov	r8, r8
 454              	.L14:
 455              		.loc 1 215 0 is_stmt 0 discriminator 1
 456 0130 244B     		ldr	r3, .L15+36
 457 0132 9B79     		ldrb	r3, [r3, #6]
 458 0134 DBB2     		uxtb	r3, r3
 459 0136 1A1C     		mov	r2, r3
 460 0138 0C23     		mov	r3, #12
 461 013a 1340     		and	r3, r2
 462 013c 0C2B     		cmp	r3, #12
 463 013e F7D1     		bne	.L14
 216:../DSP/Device/device.c **** 	  }
 217:../DSP/Device/device.c **** 	  /* Initialization of the RTC_CLKIN pin */
 218:../DSP/Device/device.c **** 	  /* PORTC_PCR1: ISF=0,MUX=1 */
 219:../DSP/Device/device.c **** 	  PORTC_PCR1 = (uint32_t)((PORTC_PCR1 & (uint32_t)~(uint32_t)(
 464              		.loc 1 219 0 is_stmt 1
 465 0140 224B     		ldr	r3, .L15+44
 466 0142 224A     		ldr	r2, .L15+44
 467 0144 5168     		ldr	r1, [r2, #4]
 468 0146 1E4A     		ldr	r2, .L15+32
 469 0148 0A40     		and	r2, r1
 470 014a 8021     		mov	r1, #128
 471 014c 4900     		lsl	r1, r1, #1
 472 014e 0A43     		orr	r2, r1
 473 0150 5A60     		str	r2, [r3, #4]
 220:../DSP/Device/device.c **** 	                PORT_PCR_ISF_MASK |
 221:../DSP/Device/device.c **** 	                PORT_PCR_MUX(0x06)
 222:../DSP/Device/device.c **** 	               )) | (uint32_t)(
 223:../DSP/Device/device.c **** 	                PORT_PCR_MUX(0x01)
 224:../DSP/Device/device.c **** 	               ));
 225:../DSP/Device/device.c **** 
 226:../DSP/Device/device.c **** 	  /*-- Update clock cfg --*/
 227:../DSP/Device/device.c **** 	  DeviceClock.MCGIRCLKClockFreq = 32768;
 474              		.loc 1 227 0
 475 0152 1F4B     		ldr	r3, .L15+48
 476 0154 8022     		mov	r2, #128
 477 0156 1202     		lsl	r2, r2, #8
 478 0158 1A60     		str	r2, [r3]
 228:../DSP/Device/device.c **** 	  DeviceClock.coreClockFreq = 48000000;
 479              		.loc 1 228 0
 480 015a 1D4B     		ldr	r3, .L15+48
 481 015c 1D4A     		ldr	r2, .L15+52
 482 015e 5A60     		str	r2, [r3, #4]
 229:../DSP/Device/device.c **** 	  DeviceClock.platformClockFreq = 48000000;
 483              		.loc 1 229 0
 484 0160 1B4B     		ldr	r3, .L15+48
 485 0162 1C4A     		ldr	r2, .L15+52
 486 0164 9A60     		str	r2, [r3, #8]
 230:../DSP/Device/device.c **** 	  DeviceClock.systemClockFreq = 48000000;
 487              		.loc 1 230 0
 488 0166 1A4B     		ldr	r3, .L15+48
 489 0168 1A4A     		ldr	r2, .L15+52
 490 016a DA60     		str	r2, [r3, #12]
 231:../DSP/Device/device.c **** 	  DeviceClock.busClockFreq = 24000000;
 491              		.loc 1 231 0
 492 016c 184B     		ldr	r3, .L15+48
 493 016e 1A4A     		ldr	r2, .L15+56
 494 0170 1A61     		str	r2, [r3, #16]
 232:../DSP/Device/device.c **** 	  DeviceClock.flashClockFreq = 24000000;
 495              		.loc 1 232 0
 496 0172 174B     		ldr	r3, .L15+48
 497 0174 184A     		ldr	r2, .L15+56
 498 0176 5A61     		str	r2, [r3, #20]
 233:../DSP/Device/device.c **** 	  DeviceClock.masterPeripheralClockFreq = 24000000;
 499              		.loc 1 233 0
 500 0178 154B     		ldr	r3, .L15+48
 501 017a 174A     		ldr	r2, .L15+56
 502 017c 9A61     		str	r2, [r3, #24]
 234:../DSP/Device/device.c **** 	  DeviceClock.OSCERCLKClockFreq = 16000000;
 503              		.loc 1 234 0
 504 017e 144B     		ldr	r3, .L15+48
 505 0180 164A     		ldr	r2, .L15+60
 506 0182 DA61     		str	r2, [r3, #28]
 235:../DSP/Device/device.c **** 	  DeviceClock.ERCLK32KClockFreq = 32768;
 507              		.loc 1 235 0
 508 0184 124B     		ldr	r3, .L15+48
 509 0186 8022     		mov	r2, #128
 510 0188 1202     		lsl	r2, r2, #8
 511 018a 1A62     		str	r2, [r3, #32]
 236:../DSP/Device/device.c **** 	  DeviceClock.LowPowerOscillatorFreq = 1000;
 512              		.loc 1 236 0
 513 018c 104B     		ldr	r3, .L15+48
 514 018e FA22     		mov	r2, #250
 515 0190 9200     		lsl	r2, r2, #2
 516 0192 5A62     		str	r2, [r3, #36]
 237:../DSP/Device/device.c **** 	  DeviceClock.RtcClockOutFreq = 0;
 517              		.loc 1 237 0
 518 0194 0E4B     		ldr	r3, .L15+48
 519 0196 0022     		mov	r2, #0
 520 0198 9A62     		str	r2, [r3, #40]
 238:../DSP/Device/device.c **** }
 521              		.loc 1 238 0
 522 019a BD46     		mov	sp, r7
 523              		@ sp needed
 524 019c 80BD     		pop	{r7, pc}
 525              	.L16:
 526 019e C046     		.align	2
 527              	.L15:
 528 01a0 00700440 		.word	1074032640
 529 01a4 44100000 		.word	4164
 530 01a8 38100000 		.word	4152
 531 01ac 00D00740 		.word	1074253824
 532 01b0 04100000 		.word	4100
 533 01b4 FFFFF3FF 		.word	-786433
 534 01b8 FFFFFFFC 		.word	-50331649
 535 01bc 00900440 		.word	1074040832
 536 01c0 FFF8FFFE 		.word	-16779009
 537 01c4 00400640 		.word	1074151424
 538 01c8 00500640 		.word	1074155520
 539 01cc 00B00440 		.word	1074049024
 540 01d0 00000000 		.word	DeviceClock
 541 01d4 006CDC02 		.word	48000000
 542 01d8 00366E01 		.word	24000000
 543 01dc 0024F400 		.word	16000000
 544              		.cfi_endproc
 545              	.LFE35:
 547              		.section	.text.LPM_Sleep,"ax",%progbits
 548              		.align	2
 549              		.global	LPM_Sleep
 550              		.code	16
 551              		.thumb_func
 553              	LPM_Sleep:
 554              	.LFB36:
 239:../DSP/Device/device.c **** 
 240:../DSP/Device/device.c **** 
 241:../DSP/Device/device.c **** void LPM_Sleep (void) {
 555              		.loc 1 241 0
 556              		.cfi_startproc
 557 0000 80B5     		push	{r7, lr}
 558              		.cfi_def_cfa_offset 8
 559              		.cfi_offset 7, -8
 560              		.cfi_offset 14, -4
 561 0002 00AF     		add	r7, sp, #0
 562              		.cfi_def_cfa_register 7
 242:../DSP/Device/device.c **** /* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep)
 243:../DSP/Device/device.c ****  * mode instead of deep sleep.
 244:../DSP/Device/device.c ****  */
 245:../DSP/Device/device.c **** 	SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
 563              		.loc 1 245 0
 564 0004 044B     		ldr	r3, .L18
 565 0006 044A     		ldr	r2, .L18
 566 0008 1269     		ldr	r2, [r2, #16]
 567 000a 0421     		mov	r1, #4
 568 000c 8A43     		bic	r2, r1
 569 000e 1A61     		str	r2, [r3, #16]
 570              	.LBB6:
 571              	.LBB7:
 572              		.file 2 "../DSP/Processor/core_cmInstr.h"
   1:../DSP/Processor/core_cmInstr.h **** /**************************************************************************//**
   2:../DSP/Processor/core_cmInstr.h ****  * @file     core_cmInstr.h
   3:../DSP/Processor/core_cmInstr.h ****  * @brief    CMSIS Cortex-M Core Instruction Access Header File
   4:../DSP/Processor/core_cmInstr.h ****  * @version  V3.30
   5:../DSP/Processor/core_cmInstr.h ****  * @date     17. February 2014
   6:../DSP/Processor/core_cmInstr.h ****  *
   7:../DSP/Processor/core_cmInstr.h ****  * @note
   8:../DSP/Processor/core_cmInstr.h ****  *
   9:../DSP/Processor/core_cmInstr.h ****  ******************************************************************************/
  10:../DSP/Processor/core_cmInstr.h **** /* Copyright (c) 2009 - 2014 ARM LIMITED
  11:../DSP/Processor/core_cmInstr.h **** 
  12:../DSP/Processor/core_cmInstr.h ****    All rights reserved.
  13:../DSP/Processor/core_cmInstr.h ****    Redistribution and use in source and binary forms, with or without
  14:../DSP/Processor/core_cmInstr.h ****    modification, are permitted provided that the following conditions are met:
  15:../DSP/Processor/core_cmInstr.h ****    - Redistributions of source code must retain the above copyright
  16:../DSP/Processor/core_cmInstr.h ****      notice, this list of conditions and the following disclaimer.
  17:../DSP/Processor/core_cmInstr.h ****    - Redistributions in binary form must reproduce the above copyright
  18:../DSP/Processor/core_cmInstr.h ****      notice, this list of conditions and the following disclaimer in the
  19:../DSP/Processor/core_cmInstr.h ****      documentation and/or other materials provided with the distribution.
  20:../DSP/Processor/core_cmInstr.h ****    - Neither the name of ARM nor the names of its contributors may be used
  21:../DSP/Processor/core_cmInstr.h ****      to endorse or promote products derived from this software without
  22:../DSP/Processor/core_cmInstr.h ****      specific prior written permission.
  23:../DSP/Processor/core_cmInstr.h ****    *
  24:../DSP/Processor/core_cmInstr.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25:../DSP/Processor/core_cmInstr.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26:../DSP/Processor/core_cmInstr.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27:../DSP/Processor/core_cmInstr.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  28:../DSP/Processor/core_cmInstr.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29:../DSP/Processor/core_cmInstr.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30:../DSP/Processor/core_cmInstr.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31:../DSP/Processor/core_cmInstr.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32:../DSP/Processor/core_cmInstr.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33:../DSP/Processor/core_cmInstr.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34:../DSP/Processor/core_cmInstr.h ****    POSSIBILITY OF SUCH DAMAGE.
  35:../DSP/Processor/core_cmInstr.h ****    ---------------------------------------------------------------------------*/
  36:../DSP/Processor/core_cmInstr.h **** 
  37:../DSP/Processor/core_cmInstr.h **** 
  38:../DSP/Processor/core_cmInstr.h **** #ifndef __CORE_CMINSTR_H
  39:../DSP/Processor/core_cmInstr.h **** #define __CORE_CMINSTR_H
  40:../DSP/Processor/core_cmInstr.h **** 
  41:../DSP/Processor/core_cmInstr.h **** 
  42:../DSP/Processor/core_cmInstr.h **** /* ##########################  Core Instruction Access  ######################### */
  43:../DSP/Processor/core_cmInstr.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  44:../DSP/Processor/core_cmInstr.h ****   Access to dedicated instructions
  45:../DSP/Processor/core_cmInstr.h ****   @{
  46:../DSP/Processor/core_cmInstr.h **** */
  47:../DSP/Processor/core_cmInstr.h **** 
  48:../DSP/Processor/core_cmInstr.h **** #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
  49:../DSP/Processor/core_cmInstr.h **** /* ARM armcc specific functions */
  50:../DSP/Processor/core_cmInstr.h **** 
  51:../DSP/Processor/core_cmInstr.h **** #if (__ARMCC_VERSION < 400677)
  52:../DSP/Processor/core_cmInstr.h ****   #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
  53:../DSP/Processor/core_cmInstr.h **** #endif
  54:../DSP/Processor/core_cmInstr.h **** 
  55:../DSP/Processor/core_cmInstr.h **** 
  56:../DSP/Processor/core_cmInstr.h **** /** \brief  No Operation
  57:../DSP/Processor/core_cmInstr.h **** 
  58:../DSP/Processor/core_cmInstr.h ****     No Operation does nothing. This instruction can be used for code alignment purposes.
  59:../DSP/Processor/core_cmInstr.h ****  */
  60:../DSP/Processor/core_cmInstr.h **** #define __NOP                             __nop
  61:../DSP/Processor/core_cmInstr.h **** 
  62:../DSP/Processor/core_cmInstr.h **** 
  63:../DSP/Processor/core_cmInstr.h **** /** \brief  Wait For Interrupt
  64:../DSP/Processor/core_cmInstr.h **** 
  65:../DSP/Processor/core_cmInstr.h ****     Wait For Interrupt is a hint instruction that suspends execution
  66:../DSP/Processor/core_cmInstr.h ****     until one of a number of events occurs.
  67:../DSP/Processor/core_cmInstr.h ****  */
  68:../DSP/Processor/core_cmInstr.h **** #define __WFI                             __wfi
  69:../DSP/Processor/core_cmInstr.h **** 
  70:../DSP/Processor/core_cmInstr.h **** 
  71:../DSP/Processor/core_cmInstr.h **** /** \brief  Wait For Event
  72:../DSP/Processor/core_cmInstr.h **** 
  73:../DSP/Processor/core_cmInstr.h ****     Wait For Event is a hint instruction that permits the processor to enter
  74:../DSP/Processor/core_cmInstr.h ****     a low-power state until one of a number of events occurs.
  75:../DSP/Processor/core_cmInstr.h ****  */
  76:../DSP/Processor/core_cmInstr.h **** #define __WFE                             __wfe
  77:../DSP/Processor/core_cmInstr.h **** 
  78:../DSP/Processor/core_cmInstr.h **** 
  79:../DSP/Processor/core_cmInstr.h **** /** \brief  Send Event
  80:../DSP/Processor/core_cmInstr.h **** 
  81:../DSP/Processor/core_cmInstr.h ****     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  82:../DSP/Processor/core_cmInstr.h ****  */
  83:../DSP/Processor/core_cmInstr.h **** #define __SEV                             __sev
  84:../DSP/Processor/core_cmInstr.h **** 
  85:../DSP/Processor/core_cmInstr.h **** 
  86:../DSP/Processor/core_cmInstr.h **** /** \brief  Instruction Synchronization Barrier
  87:../DSP/Processor/core_cmInstr.h **** 
  88:../DSP/Processor/core_cmInstr.h ****     Instruction Synchronization Barrier flushes the pipeline in the processor,
  89:../DSP/Processor/core_cmInstr.h ****     so that all instructions following the ISB are fetched from cache or
  90:../DSP/Processor/core_cmInstr.h ****     memory, after the instruction has been completed.
  91:../DSP/Processor/core_cmInstr.h ****  */
  92:../DSP/Processor/core_cmInstr.h **** #define __ISB()                           __isb(0xF)
  93:../DSP/Processor/core_cmInstr.h **** 
  94:../DSP/Processor/core_cmInstr.h **** 
  95:../DSP/Processor/core_cmInstr.h **** /** \brief  Data Synchronization Barrier
  96:../DSP/Processor/core_cmInstr.h **** 
  97:../DSP/Processor/core_cmInstr.h ****     This function acts as a special kind of Data Memory Barrier.
  98:../DSP/Processor/core_cmInstr.h ****     It completes when all explicit memory accesses before this instruction complete.
  99:../DSP/Processor/core_cmInstr.h ****  */
 100:../DSP/Processor/core_cmInstr.h **** #define __DSB()                           __dsb(0xF)
 101:../DSP/Processor/core_cmInstr.h **** 
 102:../DSP/Processor/core_cmInstr.h **** 
 103:../DSP/Processor/core_cmInstr.h **** /** \brief  Data Memory Barrier
 104:../DSP/Processor/core_cmInstr.h **** 
 105:../DSP/Processor/core_cmInstr.h ****     This function ensures the apparent order of the explicit memory operations before
 106:../DSP/Processor/core_cmInstr.h ****     and after the instruction, without ensuring their completion.
 107:../DSP/Processor/core_cmInstr.h ****  */
 108:../DSP/Processor/core_cmInstr.h **** #define __DMB()                           __dmb(0xF)
 109:../DSP/Processor/core_cmInstr.h **** 
 110:../DSP/Processor/core_cmInstr.h **** 
 111:../DSP/Processor/core_cmInstr.h **** /** \brief  Reverse byte order (32 bit)
 112:../DSP/Processor/core_cmInstr.h **** 
 113:../DSP/Processor/core_cmInstr.h ****     This function reverses the byte order in integer value.
 114:../DSP/Processor/core_cmInstr.h **** 
 115:../DSP/Processor/core_cmInstr.h ****     \param [in]    value  Value to reverse
 116:../DSP/Processor/core_cmInstr.h ****     \return               Reversed value
 117:../DSP/Processor/core_cmInstr.h ****  */
 118:../DSP/Processor/core_cmInstr.h **** #define __REV                             __rev
 119:../DSP/Processor/core_cmInstr.h **** 
 120:../DSP/Processor/core_cmInstr.h **** 
 121:../DSP/Processor/core_cmInstr.h **** /** \brief  Reverse byte order (16 bit)
 122:../DSP/Processor/core_cmInstr.h **** 
 123:../DSP/Processor/core_cmInstr.h ****     This function reverses the byte order in two unsigned short values.
 124:../DSP/Processor/core_cmInstr.h **** 
 125:../DSP/Processor/core_cmInstr.h ****     \param [in]    value  Value to reverse
 126:../DSP/Processor/core_cmInstr.h ****     \return               Reversed value
 127:../DSP/Processor/core_cmInstr.h ****  */
 128:../DSP/Processor/core_cmInstr.h **** #ifndef __NO_EMBEDDED_ASM
 129:../DSP/Processor/core_cmInstr.h **** __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 130:../DSP/Processor/core_cmInstr.h **** {
 131:../DSP/Processor/core_cmInstr.h ****   rev16 r0, r0
 132:../DSP/Processor/core_cmInstr.h ****   bx lr
 133:../DSP/Processor/core_cmInstr.h **** }
 134:../DSP/Processor/core_cmInstr.h **** #endif
 135:../DSP/Processor/core_cmInstr.h **** 
 136:../DSP/Processor/core_cmInstr.h **** /** \brief  Reverse byte order in signed short value
 137:../DSP/Processor/core_cmInstr.h **** 
 138:../DSP/Processor/core_cmInstr.h ****     This function reverses the byte order in a signed short value with sign extension to integer.
 139:../DSP/Processor/core_cmInstr.h **** 
 140:../DSP/Processor/core_cmInstr.h ****     \param [in]    value  Value to reverse
 141:../DSP/Processor/core_cmInstr.h ****     \return               Reversed value
 142:../DSP/Processor/core_cmInstr.h ****  */
 143:../DSP/Processor/core_cmInstr.h **** #ifndef __NO_EMBEDDED_ASM
 144:../DSP/Processor/core_cmInstr.h **** __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
 145:../DSP/Processor/core_cmInstr.h **** {
 146:../DSP/Processor/core_cmInstr.h ****   revsh r0, r0
 147:../DSP/Processor/core_cmInstr.h ****   bx lr
 148:../DSP/Processor/core_cmInstr.h **** }
 149:../DSP/Processor/core_cmInstr.h **** #endif
 150:../DSP/Processor/core_cmInstr.h **** 
 151:../DSP/Processor/core_cmInstr.h **** 
 152:../DSP/Processor/core_cmInstr.h **** /** \brief  Rotate Right in unsigned value (32 bit)
 153:../DSP/Processor/core_cmInstr.h **** 
 154:../DSP/Processor/core_cmInstr.h ****     This function Rotate Right (immediate) provides the value of the contents of a register rotated
 155:../DSP/Processor/core_cmInstr.h **** 
 156:../DSP/Processor/core_cmInstr.h ****     \param [in]    value  Value to rotate
 157:../DSP/Processor/core_cmInstr.h ****     \param [in]    value  Number of Bits to rotate
 158:../DSP/Processor/core_cmInstr.h ****     \return               Rotated value
 159:../DSP/Processor/core_cmInstr.h ****  */
 160:../DSP/Processor/core_cmInstr.h **** #define __ROR                             __ror
 161:../DSP/Processor/core_cmInstr.h **** 
 162:../DSP/Processor/core_cmInstr.h **** 
 163:../DSP/Processor/core_cmInstr.h **** /** \brief  Breakpoint
 164:../DSP/Processor/core_cmInstr.h **** 
 165:../DSP/Processor/core_cmInstr.h ****     This function causes the processor to enter Debug state.
 166:../DSP/Processor/core_cmInstr.h ****     Debug tools can use this to investigate system state when the instruction at a particular addre
 167:../DSP/Processor/core_cmInstr.h **** 
 168:../DSP/Processor/core_cmInstr.h ****     \param [in]    value  is ignored by the processor.
 169:../DSP/Processor/core_cmInstr.h ****                    If required, a debugger can use it to store additional information about the bre
 170:../DSP/Processor/core_cmInstr.h ****  */
 171:../DSP/Processor/core_cmInstr.h **** #define __BKPT(value)                       __breakpoint(value)
 172:../DSP/Processor/core_cmInstr.h **** 
 173:../DSP/Processor/core_cmInstr.h **** 
 174:../DSP/Processor/core_cmInstr.h **** #if       (__CORTEX_M >= 0x03)
 175:../DSP/Processor/core_cmInstr.h **** 
 176:../DSP/Processor/core_cmInstr.h **** /** \brief  Reverse bit order of value
 177:../DSP/Processor/core_cmInstr.h **** 
 178:../DSP/Processor/core_cmInstr.h ****     This function reverses the bit order of the given value.
 179:../DSP/Processor/core_cmInstr.h **** 
 180:../DSP/Processor/core_cmInstr.h ****     \param [in]    value  Value to reverse
 181:../DSP/Processor/core_cmInstr.h ****     \return               Reversed value
 182:../DSP/Processor/core_cmInstr.h ****  */
 183:../DSP/Processor/core_cmInstr.h **** #define __RBIT                            __rbit
 184:../DSP/Processor/core_cmInstr.h **** 
 185:../DSP/Processor/core_cmInstr.h **** 
 186:../DSP/Processor/core_cmInstr.h **** /** \brief  LDR Exclusive (8 bit)
 187:../DSP/Processor/core_cmInstr.h **** 
 188:../DSP/Processor/core_cmInstr.h ****     This function performs a exclusive LDR command for 8 bit value.
 189:../DSP/Processor/core_cmInstr.h **** 
 190:../DSP/Processor/core_cmInstr.h ****     \param [in]    ptr  Pointer to data
 191:../DSP/Processor/core_cmInstr.h ****     \return             value of type uint8_t at (*ptr)
 192:../DSP/Processor/core_cmInstr.h ****  */
 193:../DSP/Processor/core_cmInstr.h **** #define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
 194:../DSP/Processor/core_cmInstr.h **** 
 195:../DSP/Processor/core_cmInstr.h **** 
 196:../DSP/Processor/core_cmInstr.h **** /** \brief  LDR Exclusive (16 bit)
 197:../DSP/Processor/core_cmInstr.h **** 
 198:../DSP/Processor/core_cmInstr.h ****     This function performs a exclusive LDR command for 16 bit values.
 199:../DSP/Processor/core_cmInstr.h **** 
 200:../DSP/Processor/core_cmInstr.h ****     \param [in]    ptr  Pointer to data
 201:../DSP/Processor/core_cmInstr.h ****     \return        value of type uint16_t at (*ptr)
 202:../DSP/Processor/core_cmInstr.h ****  */
 203:../DSP/Processor/core_cmInstr.h **** #define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
 204:../DSP/Processor/core_cmInstr.h **** 
 205:../DSP/Processor/core_cmInstr.h **** 
 206:../DSP/Processor/core_cmInstr.h **** /** \brief  LDR Exclusive (32 bit)
 207:../DSP/Processor/core_cmInstr.h **** 
 208:../DSP/Processor/core_cmInstr.h ****     This function performs a exclusive LDR command for 32 bit values.
 209:../DSP/Processor/core_cmInstr.h **** 
 210:../DSP/Processor/core_cmInstr.h ****     \param [in]    ptr  Pointer to data
 211:../DSP/Processor/core_cmInstr.h ****     \return        value of type uint32_t at (*ptr)
 212:../DSP/Processor/core_cmInstr.h ****  */
 213:../DSP/Processor/core_cmInstr.h **** #define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
 214:../DSP/Processor/core_cmInstr.h **** 
 215:../DSP/Processor/core_cmInstr.h **** 
 216:../DSP/Processor/core_cmInstr.h **** /** \brief  STR Exclusive (8 bit)
 217:../DSP/Processor/core_cmInstr.h **** 
 218:../DSP/Processor/core_cmInstr.h ****     This function performs a exclusive STR command for 8 bit values.
 219:../DSP/Processor/core_cmInstr.h **** 
 220:../DSP/Processor/core_cmInstr.h ****     \param [in]  value  Value to store
 221:../DSP/Processor/core_cmInstr.h ****     \param [in]    ptr  Pointer to location
 222:../DSP/Processor/core_cmInstr.h ****     \return          0  Function succeeded
 223:../DSP/Processor/core_cmInstr.h ****     \return          1  Function failed
 224:../DSP/Processor/core_cmInstr.h ****  */
 225:../DSP/Processor/core_cmInstr.h **** #define __STREXB(value, ptr)              __strex(value, ptr)
 226:../DSP/Processor/core_cmInstr.h **** 
 227:../DSP/Processor/core_cmInstr.h **** 
 228:../DSP/Processor/core_cmInstr.h **** /** \brief  STR Exclusive (16 bit)
 229:../DSP/Processor/core_cmInstr.h **** 
 230:../DSP/Processor/core_cmInstr.h ****     This function performs a exclusive STR command for 16 bit values.
 231:../DSP/Processor/core_cmInstr.h **** 
 232:../DSP/Processor/core_cmInstr.h ****     \param [in]  value  Value to store
 233:../DSP/Processor/core_cmInstr.h ****     \param [in]    ptr  Pointer to location
 234:../DSP/Processor/core_cmInstr.h ****     \return          0  Function succeeded
 235:../DSP/Processor/core_cmInstr.h ****     \return          1  Function failed
 236:../DSP/Processor/core_cmInstr.h ****  */
 237:../DSP/Processor/core_cmInstr.h **** #define __STREXH(value, ptr)              __strex(value, ptr)
 238:../DSP/Processor/core_cmInstr.h **** 
 239:../DSP/Processor/core_cmInstr.h **** 
 240:../DSP/Processor/core_cmInstr.h **** /** \brief  STR Exclusive (32 bit)
 241:../DSP/Processor/core_cmInstr.h **** 
 242:../DSP/Processor/core_cmInstr.h ****     This function performs a exclusive STR command for 32 bit values.
 243:../DSP/Processor/core_cmInstr.h **** 
 244:../DSP/Processor/core_cmInstr.h ****     \param [in]  value  Value to store
 245:../DSP/Processor/core_cmInstr.h ****     \param [in]    ptr  Pointer to location
 246:../DSP/Processor/core_cmInstr.h ****     \return          0  Function succeeded
 247:../DSP/Processor/core_cmInstr.h ****     \return          1  Function failed
 248:../DSP/Processor/core_cmInstr.h ****  */
 249:../DSP/Processor/core_cmInstr.h **** #define __STREXW(value, ptr)              __strex(value, ptr)
 250:../DSP/Processor/core_cmInstr.h **** 
 251:../DSP/Processor/core_cmInstr.h **** 
 252:../DSP/Processor/core_cmInstr.h **** /** \brief  Remove the exclusive lock
 253:../DSP/Processor/core_cmInstr.h **** 
 254:../DSP/Processor/core_cmInstr.h ****     This function removes the exclusive lock which is created by LDREX.
 255:../DSP/Processor/core_cmInstr.h **** 
 256:../DSP/Processor/core_cmInstr.h ****  */
 257:../DSP/Processor/core_cmInstr.h **** #define __CLREX                           __clrex
 258:../DSP/Processor/core_cmInstr.h **** 
 259:../DSP/Processor/core_cmInstr.h **** 
 260:../DSP/Processor/core_cmInstr.h **** /** \brief  Signed Saturate
 261:../DSP/Processor/core_cmInstr.h **** 
 262:../DSP/Processor/core_cmInstr.h ****     This function saturates a signed value.
 263:../DSP/Processor/core_cmInstr.h **** 
 264:../DSP/Processor/core_cmInstr.h ****     \param [in]  value  Value to be saturated
 265:../DSP/Processor/core_cmInstr.h ****     \param [in]    sat  Bit position to saturate to (1..32)
 266:../DSP/Processor/core_cmInstr.h ****     \return             Saturated value
 267:../DSP/Processor/core_cmInstr.h ****  */
 268:../DSP/Processor/core_cmInstr.h **** #define __SSAT                            __ssat
 269:../DSP/Processor/core_cmInstr.h **** 
 270:../DSP/Processor/core_cmInstr.h **** 
 271:../DSP/Processor/core_cmInstr.h **** /** \brief  Unsigned Saturate
 272:../DSP/Processor/core_cmInstr.h **** 
 273:../DSP/Processor/core_cmInstr.h ****     This function saturates an unsigned value.
 274:../DSP/Processor/core_cmInstr.h **** 
 275:../DSP/Processor/core_cmInstr.h ****     \param [in]  value  Value to be saturated
 276:../DSP/Processor/core_cmInstr.h ****     \param [in]    sat  Bit position to saturate to (0..31)
 277:../DSP/Processor/core_cmInstr.h ****     \return             Saturated value
 278:../DSP/Processor/core_cmInstr.h ****  */
 279:../DSP/Processor/core_cmInstr.h **** #define __USAT                            __usat
 280:../DSP/Processor/core_cmInstr.h **** 
 281:../DSP/Processor/core_cmInstr.h **** 
 282:../DSP/Processor/core_cmInstr.h **** /** \brief  Count leading zeros
 283:../DSP/Processor/core_cmInstr.h **** 
 284:../DSP/Processor/core_cmInstr.h ****     This function counts the number of leading zeros of a data value.
 285:../DSP/Processor/core_cmInstr.h **** 
 286:../DSP/Processor/core_cmInstr.h ****     \param [in]  value  Value to count the leading zeros
 287:../DSP/Processor/core_cmInstr.h ****     \return             number of leading zeros in value
 288:../DSP/Processor/core_cmInstr.h ****  */
 289:../DSP/Processor/core_cmInstr.h **** #define __CLZ                             __clz
 290:../DSP/Processor/core_cmInstr.h **** 
 291:../DSP/Processor/core_cmInstr.h **** #endif /* (__CORTEX_M >= 0x03) */
 292:../DSP/Processor/core_cmInstr.h **** 
 293:../DSP/Processor/core_cmInstr.h **** 
 294:../DSP/Processor/core_cmInstr.h **** #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 295:../DSP/Processor/core_cmInstr.h **** /* GNU gcc specific functions */
 296:../DSP/Processor/core_cmInstr.h **** 
 297:../DSP/Processor/core_cmInstr.h **** /* Define macros for porting to both thumb1 and thumb2.
 298:../DSP/Processor/core_cmInstr.h ****  * For thumb1, use low register (r0-r7), specified by constrant "l"
 299:../DSP/Processor/core_cmInstr.h ****  * Otherwise, use general registers, specified by constrant "r" */
 300:../DSP/Processor/core_cmInstr.h **** #if defined (__thumb__) && !defined (__thumb2__)
 301:../DSP/Processor/core_cmInstr.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 302:../DSP/Processor/core_cmInstr.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 303:../DSP/Processor/core_cmInstr.h **** #else
 304:../DSP/Processor/core_cmInstr.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 305:../DSP/Processor/core_cmInstr.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 306:../DSP/Processor/core_cmInstr.h **** #endif
 307:../DSP/Processor/core_cmInstr.h **** 
 308:../DSP/Processor/core_cmInstr.h **** /** \brief  No Operation
 309:../DSP/Processor/core_cmInstr.h **** 
 310:../DSP/Processor/core_cmInstr.h ****     No Operation does nothing. This instruction can be used for code alignment purposes.
 311:../DSP/Processor/core_cmInstr.h ****  */
 312:../DSP/Processor/core_cmInstr.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
 313:../DSP/Processor/core_cmInstr.h **** {
 314:../DSP/Processor/core_cmInstr.h ****   __ASM volatile ("nop");
 315:../DSP/Processor/core_cmInstr.h **** }
 316:../DSP/Processor/core_cmInstr.h **** 
 317:../DSP/Processor/core_cmInstr.h **** 
 318:../DSP/Processor/core_cmInstr.h **** /** \brief  Wait For Interrupt
 319:../DSP/Processor/core_cmInstr.h **** 
 320:../DSP/Processor/core_cmInstr.h ****     Wait For Interrupt is a hint instruction that suspends execution
 321:../DSP/Processor/core_cmInstr.h ****     until one of a number of events occurs.
 322:../DSP/Processor/core_cmInstr.h ****  */
 323:../DSP/Processor/core_cmInstr.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
 324:../DSP/Processor/core_cmInstr.h **** {
 325:../DSP/Processor/core_cmInstr.h ****   __ASM volatile ("wfi");
 573              		.loc 2 325 0
 574              	@ 325 "../DSP/Processor/core_cmInstr.h" 1
 575 0010 30BF     		wfi
 576              	@ 0 "" 2
 577              		.code	16
 578              	.LBE7:
 579              	.LBE6:
 246:../DSP/Device/device.c **** 	WakeFromInterrupt();
 247:../DSP/Device/device.c **** }
 580              		.loc 1 247 0
 581 0012 BD46     		mov	sp, r7
 582              		@ sp needed
 583 0014 80BD     		pop	{r7, pc}
 584              	.L19:
 585 0016 C046     		.align	2
 586              	.L18:
 587 0018 00ED00E0 		.word	-536810240
 588              		.cfi_endproc
 589              	.LFE36:
 591              		.section	.text.LPM_DeepSleep,"ax",%progbits
 592              		.align	2
 593              		.global	LPM_DeepSleep
 594              		.code	16
 595              		.thumb_func
 597              	LPM_DeepSleep:
 598              	.LFB37:
 248:../DSP/Device/device.c **** 
 249:../DSP/Device/device.c **** 
 250:../DSP/Device/device.c **** void LPM_DeepSleep (void) {
 599              		.loc 1 250 0
 600              		.cfi_startproc
 601 0000 80B5     		push	{r7, lr}
 602              		.cfi_def_cfa_offset 8
 603              		.cfi_offset 7, -8
 604              		.cfi_offset 14, -4
 605 0002 00AF     		add	r7, sp, #0
 606              		.cfi_def_cfa_register 7
 251:../DSP/Device/device.c **** 	/*=== Set the SLEEPDEEP bit to enable deep sleep mode (STOP) ===*/
 252:../DSP/Device/device.c **** 	 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 607              		.loc 1 252 0
 608 0004 044B     		ldr	r3, .L21
 609 0006 044A     		ldr	r2, .L21
 610 0008 1269     		ldr	r2, [r2, #16]
 611 000a 0421     		mov	r1, #4
 612 000c 0A43     		orr	r2, r1
 613 000e 1A61     		str	r2, [r3, #16]
 614              	.LBB8:
 615              	.LBB9:
 616              		.loc 2 325 0
 617              	@ 325 "../DSP/Processor/core_cmInstr.h" 1
 618 0010 30BF     		wfi
 619              	@ 0 "" 2
 620              		.code	16
 621              	.LBE9:
 622              	.LBE8:
 253:../DSP/Device/device.c **** 	 WakeFromInterrupt();			//Enterring sleep
 254:../DSP/Device/device.c **** }
 623              		.loc 1 254 0
 624 0012 BD46     		mov	sp, r7
 625              		@ sp needed
 626 0014 80BD     		pop	{r7, pc}
 627              	.L22:
 628 0016 C046     		.align	2
 629              	.L21:
 630 0018 00ED00E0 		.word	-536810240
 631              		.cfi_endproc
 632              	.LFE37:
 634              		.section	.text.LPM_VLPS,"ax",%progbits
 635              		.align	2
 636              		.global	LPM_VLPS
 637              		.code	16
 638              		.thumb_func
 640              	LPM_VLPS:
 641              	.LFB38:
 255:../DSP/Device/device.c **** 
 256:../DSP/Device/device.c **** void LPM_VLPS (void) {
 642              		.loc 1 256 0
 643              		.cfi_startproc
 644 0000 80B5     		push	{r7, lr}
 645              		.cfi_def_cfa_offset 8
 646              		.cfi_offset 7, -8
 647              		.cfi_offset 14, -4
 648 0002 82B0     		sub	sp, sp, #8
 649              		.cfi_def_cfa_offset 16
 650 0004 00AF     		add	r7, sp, #0
 651              		.cfi_def_cfa_register 7
 257:../DSP/Device/device.c **** 	volatile unsigned int dummyread;
 258:../DSP/Device/device.c **** 	/*The PMPROT register may have already been written by init
 259:../DSP/Device/device.c ****  	 code. If so then this next write is not done since
 260:../DSP/Device/device.c ****  	 PMPROT is write once after RESET.
 261:../DSP/Device/device.c ****  	 This Write allows the MCU to enter the VLPR, VLPW,
 262:../DSP/Device/device.c ****  	 and VLPS modes. If AVLP is already written to 0
 263:../DSP/Device/device.c ****  	 Stop is entered instead of VLPS*/
 264:../DSP/Device/device.c **** 	SMC->PMPROT = SMC_PMPROT_AVLP_MASK;
 652              		.loc 1 264 0
 653 0006 0E4B     		ldr	r3, .L24
 654 0008 2022     		mov	r2, #32
 655 000a 1A70     		strb	r2, [r3]
 265:../DSP/Device/device.c **** 	/* Set the STOPM field to 0b010 for VLPS mode */
 266:../DSP/Device/device.c **** 	SMC->PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
 656              		.loc 1 266 0
 657 000c 0C4B     		ldr	r3, .L24
 658 000e 0C4A     		ldr	r2, .L24
 659 0010 5278     		ldrb	r2, [r2, #1]
 660 0012 D2B2     		uxtb	r2, r2
 661 0014 0721     		mov	r1, #7
 662 0016 8A43     		bic	r2, r1
 663 0018 D2B2     		uxtb	r2, r2
 664 001a 5A70     		strb	r2, [r3, #1]
 267:../DSP/Device/device.c **** 	SMC->PMCTRL |= SMC_PMCTRL_STOPM(0x2);
 665              		.loc 1 267 0
 666 001c 084B     		ldr	r3, .L24
 667 001e 084A     		ldr	r2, .L24
 668 0020 5278     		ldrb	r2, [r2, #1]
 669 0022 D2B2     		uxtb	r2, r2
 670 0024 0221     		mov	r1, #2
 671 0026 0A43     		orr	r2, r1
 672 0028 D2B2     		uxtb	r2, r2
 673 002a 5A70     		strb	r2, [r3, #1]
 268:../DSP/Device/device.c **** 	/*wait for write to complete to SMC before stopping core */
 269:../DSP/Device/device.c **** 	dummyread = SMC_PMCTRL;
 674              		.loc 1 269 0
 675 002c 044B     		ldr	r3, .L24
 676 002e 5B78     		ldrb	r3, [r3, #1]
 677 0030 DBB2     		uxtb	r3, r3
 678 0032 7B60     		str	r3, [r7, #4]
 270:../DSP/Device/device.c **** 	/* Now execute the stop instruction to go into VLPS */
 271:../DSP/Device/device.c **** 	LPM_DeepSleep();
 679              		.loc 1 271 0
 680 0034 FFF7FEFF 		bl	LPM_DeepSleep
 272:../DSP/Device/device.c **** }
 681              		.loc 1 272 0
 682 0038 BD46     		mov	sp, r7
 683 003a 02B0     		add	sp, sp, #8
 684              		@ sp needed
 685 003c 80BD     		pop	{r7, pc}
 686              	.L25:
 687 003e C046     		.align	2
 688              	.L24:
 689 0040 00E00740 		.word	1074257920
 690              		.cfi_endproc
 691              	.LFE38:
 693              		.text
 694              	.Letext0:
 695              		.file 3 "e:\\logiciels\\freescale\\kinetis design studio v2.0.0\\toolchain\\arm-none-eabi\\include
 696              		.file 4 "../DSP/Processor/core_cm0plus.h"
 697              		.file 5 "../DSP/Processor/MKL16Z4.h"
 698              		.file 6 "../DSP/DSP/DSP_mkl16z256vlh4.h"
DEFINED SYMBOLS
                            *ABS*:00000000 device.c
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:18     .text.DeviceInit:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:23     .text.DeviceInit:00000000 DeviceInit
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:49     .text.DeviceClockSwitchDefaultFEI:00000000 DeviceClockSwitchDefaultFEI
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:44     .text.DeviceClockSwitchDefaultFEI:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:243    .text.DeviceClockSwitchDefaultFEI:0000012c $d
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:257    .text.DeviceClockSwitchHighPower:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:262    .text.DeviceClockSwitchHighPower:00000000 DeviceClockSwitchHighPower
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:528    .text.DeviceClockSwitchHighPower:000001a0 $d
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:548    .text.LPM_Sleep:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:553    .text.LPM_Sleep:00000000 LPM_Sleep
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:587    .text.LPM_Sleep:00000018 $d
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:592    .text.LPM_DeepSleep:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:597    .text.LPM_DeepSleep:00000000 LPM_DeepSleep
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:630    .text.LPM_DeepSleep:00000018 $d
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:635    .text.LPM_VLPS:00000000 $t
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:640    .text.LPM_VLPS:00000000 LPM_VLPS
C:\Users\Thibaut\AppData\Local\Temp\cczLND7H.s:689    .text.LPM_VLPS:00000040 $d
                     .debug_frame:00000010 $d
                           .group:00000000 wm4.1.e04ac588437856bc6ef5393c7523eb9b
                           .group:00000000 wm4.MKL16Z4.h.90.bfde7d3466e2aaae63e51401b8102c97
                           .group:00000000 wm4.stdint.h.10.90b695f550ca6cc3fb08fa83baf01e05
                           .group:00000000 wm4.MKL16Z4.h.103.3e71c13f67b70bf817331938e7ca6a21
                           .group:00000000 wm4.core_cm0plus.h.43.8a4a713129c4559638c90873d349aea7
                           .group:00000000 wm4.core_cmInstr.h.39.983ab10f37e3e59f2988e58e0e4c2ffe
                           .group:00000000 wm4.core_cm0plus.h.155.59f470bcbcb3497af7bb725005dd1359
                           .group:00000000 wm4.system_MKL16Z4.h.88.72b1d1936df247599ee4cea7d4cce2ba
                           .group:00000000 wm4.MKL16Z4.h.269.abf5f141593110fd4167c1d7382def80
                           .group:00000000 wm4.DSP_mkl16z256vlh4.h.41.eda3ab3179e3d55e14f47eb53566a464
                           .group:00000000 wm4.device.h.36.60fef1305d20f53111656ac1850514f8

UNDEFINED SYMBOLS
DeviceClock
